[Intel-gfx] [PATCH 2/3] drm/i915 save render context on Ironlake

[Eric Anholt]

On Fri, 25 Jun 2010 13:40:23 +0800, Zou Nan hai <nanhai.zou at intel.com> wrote:
> RC6 requires setup logical render context
> 
> Signed-off-by: Zou Nan hai <nanhai.zou at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |    1 +
>  drivers/gpu/drm/i915/i915_reg.h      |   13 +++++++-
>  drivers/gpu/drm/i915/intel_display.c |   53 +++++++++++++++++++++++++++------
>  3 files changed, 56 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9ed8ecd..cbc8cae 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -245,6 +245,7 @@ typedef struct drm_i915_private {
>  	drm_local_map_t hws_map;
>  	struct drm_gem_object *seqno_obj;
>  	struct drm_gem_object *pwrctx;
> +	struct drm_gem_object *renderctx;
>  
>  	struct resource mch_res;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 64b0a3a..96103ae 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -176,9 +176,15 @@
>  #define   MI_OVERLAY_CONTINUE	(0x0<<21)
>  #define   MI_OVERLAY_ON		(0x1<<21)
>  #define   MI_OVERLAY_OFF	(0x2<<21)
> +#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
>  #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
>  #define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
> -#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
> +#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
> +#define   MI_MM_SPACE_GTT		(1<<8)
> +#define   MI_MM_SPACE_PHYSICAL		(0<<8)
> +#define   MI_SAVE_EXT_STATE_EN		(1<<3)
> +#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
> +#define   MI_RESTORE_INHIBIT		(1<<0)
>  #define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
>  #define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
>  #define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
> @@ -1042,6 +1048,11 @@
>  #define DDRMPLL1		0X12c20
>  #define PEG_BAND_GAP_DATA	0x14d68
>  
> +/*
> + * Logical Context regs
> + */
> +#define CCID			0x2180
> +#define   CCID_EN		(1<<0)
>  /*
>   * Overlay regs
>   */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c3c9feb..efcfda9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5026,37 +5026,37 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
>  };
>  
>  static struct drm_gem_object *
> -intel_alloc_power_context(struct drm_device *dev)
> +intel_alloc_context_page(struct drm_device *dev)
>  {
> -	struct drm_gem_object *pwrctx;
> +	struct drm_gem_object *ctx;
>  	int ret;
>  
> -	pwrctx = i915_gem_alloc_object(dev, 4096);
> -	if (!pwrctx) {
> +	ctx = i915_gem_alloc_object(dev, 4096);
> +	if (!ctx) {
>  		DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
>  		return NULL;
>  	}
>  
>  	mutex_lock(&dev->struct_mutex);
> -	ret = i915_gem_object_pin(pwrctx, 4096);
> +	ret = i915_gem_object_pin(ctx, 4096);
>  	if (ret) {
>  		DRM_ERROR("failed to pin power context: %d\n", ret);
>  		goto err_unref;
>  	}
>  
> -	ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
> +	ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
>  	if (ret) {
>  		DRM_ERROR("failed to set-domain on power context: %d\n", ret);
>  		goto err_unpin;
>  	}
>  	mutex_unlock(&dev->struct_mutex);
>  
> -	return pwrctx;
> +	return ctx;
>  
>  err_unpin:
> -	i915_gem_object_unpin(pwrctx);
> +	i915_gem_object_unpin(ctx);
>  err_unref:
> -	drm_gem_object_unreference(pwrctx);
> +	drm_gem_object_unreference(ctx);
>  	mutex_unlock(&dev->struct_mutex);
>  	return NULL;
>  }
> @@ -5343,6 +5343,29 @@ void intel_init_clock_gating(struct drm_device *dev)
>  	 * GPU can automatically power down the render unit if given a page
>  	 * to save state.
>  	 */
> +	if (IS_IRONLAKE_M(dev)) {
> +		if (dev_priv->renderctx == NULL)
> +			dev_priv->renderctx = intel_alloc_context_page(dev);
> +		if (dev_priv->renderctx) {
> +			struct drm_i915_gem_object *obj_priv;
> +			obj_priv = to_intel_bo(dev_priv->renderctx);
> +			if (obj_priv) {
> +				BEGIN_LP_RING(4);
> +				OUT_RING(MI_SET_CONTEXT);
> +				OUT_RING(obj_priv->gtt_offset |
> +						MI_MM_SPACE_GTT |
> +						MI_SAVE_EXT_STATE_EN |
> +						MI_RESTORE_EXT_STATE_EN |
> +						MI_RESTORE_INHIBIT);
> +				OUT_RING(MI_NOOP);
> +				OUT_RING(MI_FLUSH);
> +				ADVANCE_LP_RING();

I don't think you mean SAVE_EXT_STATE_EN here -- doesn't that mean store
the current state to the current context (but we haven't set a context
up yet)?

The following patch to fix hangs with this patch in place needs to come
before this patch in the series, or you'll break bisects.

(looks like my other concern wasn't a problem -- init_clock_gating() is
called again at resume time, and we don't have any 3D state we need
saved across s/r so we don't need to restore out of the context or
anything).
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