[Intel-gfx] [PATCH 11/11] drm/i915: order fence setup wrt subsequent wc cpu writes

[Chris Wilson]

On Fri, 15 Jan 2010 13:24:18 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> Similar to the cpu gtt flush. Prevent subsequent cpu wc writes to get
> reordered before the fence is set up. Also the gpu _might_ start
> executing the batchbuffer before the write has hit the fence reg
> (totally unlikely, but still).

Hmm, isn't the problem as identified much wider spread than just the
fence regs? Perhaps we should be flushing all potential register updates
prior to manipulating the ringbuffer? Or should we be setting the fence
registers using MI_IMM_DATA for gpu access, etc?
-ickle

-- 
Chris Wilson, Intel Open Source Technology Centre