[Intel-gfx] [PATCH 11/11] drm/i915: order fence setup wrt subsequent wc cpu writes

[Daniel Vetter]

On Fri, Jan 15, 2010 at 01:27:20PM +0000, Chris Wilson wrote:
> On Fri, 15 Jan 2010 13:24:18 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> > Similar to the cpu gtt flush. Prevent subsequent cpu wc writes to get
> > reordered before the fence is set up. Also the gpu _might_ start
> > executing the batchbuffer before the write has hit the fence reg
> > (totally unlikely, but still).
> 
> Hmm, isn't the problem as identified much wider spread than just the
> fence regs? Perhaps we should be flushing all potential register updates
> prior to manipulating the ringbuffer? Or should we be setting the fence
> registers using MI_IMM_DATA for gpu access, etc?

I've only crawled around in the i915_gem.c mostly. So yes, the problem
could be more widespread.

Setting the fences with the ringbuffer was an idea I've had, too. This
would be especially well-suited when we need to steal fences from
currently-executing batchbuffers. But this would also need some new
asynchronous fence tracking (like we do with obj_priv->active for the
pipelined gpu flushes). So I opted for the less-intrusive change.
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48