[Intel-gfx] [PATCH 11/11] drm/i915: order fence setup wrt subsequent wc cpu writes

[Daniel Vetter]

On Fri, Jan 15, 2010 at 02:38:27PM +0100, Daniel Vetter wrote:
> I've only crawled around in the i915_gem.c mostly. So yes, the problem
> could be more widespread.
> 
> Setting the fences with the ringbuffer was an idea I've had, too. This
> would be especially well-suited when we need to steal fences from
> currently-executing batchbuffers. But this would also need some new
> asynchronous fence tracking (like we do with obj_priv->active for the
> pipelined gpu flushes). So I opted for the less-intrusive change.

Furthermore there would be still the problem of synchronizing fence reg
changes with subsequent writes to the gtt by the cpu.
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
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