[Intel-gfx] [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965

Chris Wilson chris at chris-wilson.co.uk
Mon Jul 5 18:39:24 CEST 2010

On Mon, 05 Jul 2010 09:22:30 -0700, Eric Anholt <eric at anholt.net> wrote:
> On Mon,  5 Jul 2010 10:25:57 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > The original i965 requires an alignment of 128K for the display surface
> > with linear memory, so increase the requirement from 64k for these
> > chipsets. For the later chipsets in the i965 family, only a 4k alignment
> > is required. (So long as we do not start performing asynchronous flips.)
> > 
> > Note the impact of this should be slight as on i965 we should be using a
> > tiled frontbuffer for anything up to a 4096x4096 display.
> How about G35?  Does it apply to that, too?

In the section on DSP[AB]SURF it specifically lists the special case for
DevBW and DevCL. In which case, it would appear that the 128K alignment
applies for G35 as well.

* goes to tweak the patch.

Chris Wilson, Intel Open Source Technology Centre

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