[Intel-gfx] pitch assertion with recent mesa/libdrm on 965

[Kenneth Graunke]

Hi Eric,

I've hit a regression with Mesa 179d2c0e (intel: Use drm_intel_bo_alloc_tiled 
for region allocs.) and libdrm master.  With your mesa change, PlaneShift 
reproducibly triggers the following assertion:

intel_regions.c:193: intel_region_alloc: Assertion `aligned_pitch == pitch * 
cpp' failed.

The call trace:
#3  0x00007fffe702f374 in intel_region_alloc () from 
/usr/lib/xorg/modules/dri/i965_dri.so
#4  0x00007fffe702d82e in intel_alloc_renderbuffer_storage () from 
/usr/lib/xorg/modules/dri/i965_dri.so
#5  0x00007fffe70b4394 in renderbuffer_storage () from 
/usr/lib/xorg/modules/dri/i965_dri.so

The values in question are:
aligned_pitch == 32
pitch * cpp   == 64
width         == 8
height        == 32
pitch         == 16
cpp           == 4
tiling        == I915_TILING_NONE

In particular, it looks like Mesa's intel_region_alloc does:
pitch = ((cpp * width + 63) & ~63) / cpp;   ...and comes up with 16
while libdrm's drm_intel_gem_bo_alloc_tiled does:
stride = x * cpp;  ...and comes up with 32

These definitely compute different values; I'm not sure what the right answer 
is though.  The old version of intel_alloc_regions seemed to use an alignment 
of 64, not 32.

Thanks for looking into it.  If you need anything else, just let me know!
--Kenneth