[Intel-gfx] [PATCH 05/13] agp/intel: Use a non-reserved value for the cache field of the PTEs.

[Owain Ainsworth]

On Thu, Feb 25, 2010 at 11:09:48AM -0800, Eric Anholt wrote:
> I don't know if this is what we'll want to be using long term, we'll see.
> 
> Signed-off-by: Eric Anholt <eric at anholt.net>

Late (this has long been commited), but this doesn't actually do
anything:

we declare cache_bits, set it to a value, then do *nothing* with it.

was this intended to be ORed into the writel?

-0-
> ---
>  drivers/char/agp/intel-agp.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
> index df85ed9..c3c870b 100644
> --- a/drivers/char/agp/intel-agp.c
> +++ b/drivers/char/agp/intel-agp.c
> @@ -296,6 +296,11 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem,
>  					off_t pg_start, int mask_type)
>  {
>  	int i, j;
> +	u32 cache_bits = 0;
> +
> +	if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) {
> +		cache_bits = I830_PTE_SYSTEM_CACHED;
> +	}
>  
>  	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
>  		writel(agp_bridge->driver->mask_memory(agp_bridge,
> -- 
> 1.7.0
> 
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