[Intel-gfx] [intel-gfx][PATCH 2/2] drm/i915: Add a new ring buffer on Sandybridge

[Daniel Vetter]

On Thu, Sep 02, 2010 at 09:46:54PM +0800, Xiang, Haihao wrote:
>  /*
> + * video command stream instruction and interrupt control register defines
> + * for GEN6
> + */
> +#define GEN6_BSD_RING_TAIL		0x12030
> +#define GEN6_BSD_RING_HEAD		0x12034
> +#define GEN6_BSD_RING_START		0x12038
> +#define GEN6_BSD_RING_CTL		0x1203c
> +#define GEN6_BSD_RING_ACTHD		0x12074
> +#define GEN6_BSD_HWS_PGA		0x14080

If I'm not completely mistaken, all these ringbuffer register have the
same offsets over a common base: 0x02000 for the render ring, 0x04000 for
bsd on gen5, 0x12000 for bsd on gen6.

Can't we just store that base somewhere in intel_ring_buffer and kill all
these copy&pasted register access macros? I've played around a bit with
this, and most functions become so small it's cheaper to convert them to
inlines. This also has the potential make the other functions simpler,
perhaps even making them fully generic. Oh, and adding new ringbuffers
should becoma way easier, too (blitter ring anyone?).

At least my local hacks here where good enough to watch the lotr. If you
want I'll push them somewhere, but the patches are not really great and
definitely conflict against newer stuff.

Yours, Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48