[Intel-gfx] [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence

[Daniel Vetter]

On Tue, Apr 12, 2011 at 09:31:54PM +0100, Chris Wilson wrote:
> We only want to mark the transition from unfenced GPU access by an
> execbuffer, so that we are forced to flush any pending writes through
> the fence before updating the register.

The idea behind this change sounds good. But it completely kills the
optimization to not unnecessarily stall for fences when the fence isn't in
use anymore because we reset fenced_gpu_access = false only when moving to
the inactive list. And when flushing the fence, which is equally late.

What about moving

	fenced_gpu_access = false

from flush_fence to process_flushing_list (and replace the one in
flush_fence with an WARN_ON(fenced_gpu_access) after the flush_ring)?
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
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