[Intel-gfx] [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence

[Chris Wilson]

On Wed, 13 Apr 2011 21:37:03 +0200, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Tue, Apr 12, 2011 at 09:31:54PM +0100, Chris Wilson wrote:
> > We only want to mark the transition from unfenced GPU access by an
> > execbuffer, so that we are forced to flush any pending writes through
> > the fence before updating the register.
> 
> The idea behind this change sounds good.

Whilst I have you in agreement, what do I need to do get your r-b on the
simple bug fix first? ;-)

> But it completely kills the
> optimization to not unnecessarily stall for fences when the fence isn't in
> use anymore because we reset fenced_gpu_access = false only when moving to
> the inactive list. And when flushing the fence, which is equally late.

I'm following you so far...

> What about moving
> 
> 	fenced_gpu_access = false
> 
> from flush_fence to process_flushing_list (and replace the one in
> flush_fence with an WARN_ON(fenced_gpu_access) after the flush_ring)?

And I'm still with you. Sounds good.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre