[Intel-gfx] [PATCH] drm/i915: Seperate fence pin counting from normal bind pin counting

[Paul Menzel]

Am Samstag, den 09.07.2011, 09:25 +0100 schrieb Chris Wilson:

Whoever pushes this, please correct

s/Seperate/Separate/

in the commit summary.

> In order to correctly account for reserving space in the GTT and fences
> for a batch buffer, we need to independently track whether the fence is
> pinned due to a fenced GPU access in the batch from from whether the
> buffer is pinned in the aperture. Currently we count the fenced as

»the fenced« sounds strange. Probably I need to read up the code to
grasp that. Or is the »d« at the end a typo?

> pinned if the buffer has already been seen in the execbuffer. This leads
> to a false accounting of available fence registers, causing frequent
> mass evictions. Worse, if coupled with the change to make
> i915_gem_object_get_fence() report EDADLK upon fence starvation, the
> batchbuffer can fail with only one fence required...
> 
> Fixes intel-gpu-tools/tests/gem_fenced_exec_thrash
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38735
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> Tested-by: Paul Neumann <paul104x at yahoo.de>

[…]


Thanks,

Paul
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