[Intel-gfx] Setting proper video mode
jarek
jarek at poczta.srv.pl
Fri Nov 4 09:52:06 CET 2011
Hello!
This is the diff between intel_reg_dumper output for iegd and xf86.
Attached are full dumps.
With iegd LVDS connected display is working, with xf86 only VGA is
working.
19c19
< VCLK_POST_DIV: 0x01040104 (vga0 p1 = 6, p2 = 2, vga1 p1 = 3, p2
= 2)
---
> VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2
= 2)
26c26
< SDVOB: 0xa0480084 (enabled, pipe A, stall enabled,
detected)
---
> SDVOB: 0x80480084 (enabled, pipe A, stall disabled,
detected)
29c29
< DSPARB: 0x00002020
---
> DSPARB: 0x00001d9c
33,34c33,34
< ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
< LVDS: 0xc020033c (enabled, pipe B, 18 bit, 2 channels)
---
> ADPA: 0x00008c00 (disabled, pipe A, -hsync, -vsync)
> LVDS: 0xc0008300 (enabled, pipe B, 18 bit, 1 channel)
36c36
< DVOB: 0xa0480084 (enabled, pipe A, TV stall, -hsync,
-vsync)
---
> DVOB: 0x80480084 (enabled, pipe A, no stall, -hsync,
-vsync)
43,44c43,44
< PP_ON_DELAYS: 0x00000000
< PP_OFF_DELAYS: 0x00000000
---
> PP_ON_DELAYS: 0x025807d0
> PP_OFF_DELAYS: 0x01f407d0
46c46
< PFIT_CONTROL: 0x00000228
---
> PFIT_CONTROL: 0x80000448
48,50c48,50
< PORT_HOTPLUG_EN: 0x00000020
< PORT_HOTPLUG_STAT: 0x00000b00
< DSPACNTR: 0xd8000000 (enabled, pipe A)
---
> PORT_HOTPLUG_EN: 0x04000220
> PORT_HOTPLUG_STAT: 0x00000700
> DSPACNTR: 0xd9000000 (enabled, pipe B)
54c54
< DSPABASE: 0x00000000
---
> DSPABASE: 0x00800000
59c59
< PIPEASTAT: 0x00020203 (status: VBLANK_INT_ENABLE
VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
---
> PIPEASTAT: 0x00000000 (status:)
64c64
< CURSOR_A_BASE: 0x34eb1000
---
> CURSOR_A_BASE: 0x00000000
66,69c66,69
< CURSOR_A_POSITION: 0x8001009f
< FPA0: 0x00020f08 (n = 2, m1 = 15, m2 = 8)
< FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
< DPLL_A: 0xd4020003 (enabled, dvo, default clock,
DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
---
> CURSOR_A_POSITION: 0x00000000
> FPA0: 0x00041008 (n = 4, m1 = 16, m2 = 8)
> FPA1: 0x00041008 (n = 4, m1 = 16, m2 = 8)
> DPLL_A: 0xd4010010 (enabled, dvo, default clock,
DAC/serial mode, p1 = 1, p2 = 10, SDVO mult 2)
71,76c71,76
< HTOTAL_A: 0x0a9f077f (1920 active, 2720 total)
< HBLANK_A: 0x0a9f077f (1920 start, 2720 end)
< HSYNC_A: 0x080e07b6 (1975 start, 2063 end)
< VTOTAL_A: 0x02a701df (480 active, 680 total)
< VBLANK_A: 0x02a701df (480 start, 680 end)
< VSYNC_A: 0x01e701e2 (483 start, 488 end)
---
> HTOTAL_A: 0x066f0555 (1366 active, 1648 total)
> HBLANK_A: 0x066f0555 (1366 start, 1648 end)
> HSYNC_A: 0x0628059b (1436 start, 1577 end)
> VTOTAL_A: 0x032902ff (768 active, 810 total)
> VBLANK_A: 0x032902ff (768 start, 810 end)
> VSYNC_A: 0x030e0309 (778 start, 783 end)
79c79
< DSPBCNTR: 0xd9000000 (enabled, pipe B)
---
> DSPBCNTR: 0xd8000000 (enabled, pipe A)
83c83
< DSPBBASE: 0x00000000
---
> DSPBBASE: 0x00800000
88c88
< PIPEBSTAT: 0x00020202 (status: VBLANK_INT_ENABLE
VSYNC_INT_STATUS VBLANK_INT_STATUS)
---
> PIPEBSTAT: 0x00000000 (status:)
93c93
< CURSOR_B_BASE: 0x34eb1000
---
> CURSOR_B_BASE: 0x00000000
95,98c95,98
< CURSOR_B_POSITION: 0x8001009f
< FPB0: 0x00010b08 (n = 1, m1 = 11, m2 = 8)
< FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
< DPLL_B: 0x99046003 (enabled, non-dvo, spread spectrum
clock, LVDS mode, p1 = 3, p2 = 7, SDVO mult 1)
---
> CURSOR_B_POSITION: 0x00000000
> FPB0: 0x00010b07 (n = 1, m1 = 11, m2 = 7)
> FPB1: 0x00010b07 (n = 1, m1 = 11, m2 = 7)
> DPLL_B: 0x98406000 (enabled, non-dvo, spread spectrum
clock, LVDS mode, p1 = 7, p2 = 14, SDVO mult 1)
100,105c100,105
< HTOTAL_B: 0x0a9f077f (1920 active, 2720 total)
< HBLANK_B: 0x0a9f077f (1920 start, 2720 end)
< HSYNC_B: 0x080e07b6 (1975 start, 2063 end)
< VTOTAL_B: 0x02a701df (480 active, 680 total)
< VBLANK_B: 0x02a701df (480 start, 680 end)
< VSYNC_B: 0x01e701e2 (483 start, 488 end)
---
> HTOTAL_B: 0x030f027f (640 active, 784 total)
> HBLANK_B: 0x030f027f (640 start, 784 end)
> HSYNC_B: 0x02e70287 (648 start, 744 end)
> VTOTAL_B: 0x01fc009f (160 active, 509 total)
> VBLANK_B: 0x015c013f (320 start, 349 end)
> VSYNC_B: 0x014f014d (334 start, 336 end)
110,112c110,112
< VCLK_POST_DIV: 0x01040104
< VGACNTRL: 0x8020008e (disabled)
< TV_CTL: 0x10000010
---
> VCLK_POST_DIV: 0x00020002
> VGACNTRL: 0x80000000 (disabled)
> TV_CTL: 0x000c0010
114,133c114,133
< TV_CSC_Y: 0x00000000
< TV_CSC_Y2: 0x00000000
< TV_CSC_U: 0x00000000
< TV_CSC_U2: 0x00000000
< TV_CSC_V: 0x00000000
< TV_CSC_V2: 0x00000000
< TV_CLR_KNOBS: 0x00000000
< TV_CLR_LEVEL: 0x00000000
< TV_H_CTL_1: 0x00000000
< TV_H_CTL_2: 0x00000000
< TV_H_CTL_3: 0x00000000
< TV_V_CTL_1: 0x00000000
< TV_V_CTL_2: 0x00000000
< TV_V_CTL_3: 0x00000000
< TV_V_CTL_4: 0x00000000
< TV_V_CTL_5: 0x00000000
< TV_V_CTL_6: 0x00000000
< TV_V_CTL_7: 0x00000000
< TV_SC_CTL_1: 0x00000000
< TV_SC_CTL_2: 0x00000000
---
> TV_CSC_Y: 0x0332012d
> TV_CSC_Y2: 0x07d30104
> TV_CSC_U: 0x0733052d
> TV_CSC_U2: 0x05c70200
> TV_CSC_V: 0x0340030c
> TV_CSC_V2: 0x06d00200
> TV_CLR_KNOBS: 0x00606000
> TV_CLR_LEVEL: 0x010b00e1
> TV_H_CTL_1: 0x00400359
> TV_H_CTL_2: 0x80480022
> TV_H_CTL_3: 0x007c0344
> TV_V_CTL_1: 0x00f01415
> TV_V_CTL_2: 0x00060607
> TV_V_CTL_3: 0x80120001
> TV_V_CTL_4: 0x000900f0
> TV_V_CTL_5: 0x000a00f0
> TV_V_CTL_6: 0x000900f0
> TV_V_CTL_7: 0x000a00f0
> TV_SC_CTL_1: 0xc1710087
> TV_SC_CTL_2: 0x6b405140
135,139c135,139
< TV_WIN_POS: 0x00000000
< TV_WIN_SIZE: 0x00000000
< TV_FILTER_CTL_1: 0x00000000
< TV_FILTER_CTL_2: 0x00000000
< TV_FILTER_CTL_3: 0x00000000
---
> TV_WIN_POS: 0x00360024
> TV_WIN_SIZE: 0x02640198
> TV_FILTER_CTL_1: 0x800010bb
> TV_FILTER_CTL_2: 0x00028283
> TV_FILTER_CTL_3: 0x00014141
142,145c142,145
< TV_H_LUMA_0: 0x00000000
< TV_H_LUMA_59: 0x00000000
< TV_H_CHROMA_0: 0x00000000
< TV_H_CHROMA_59: 0x00000000
---
> TV_H_LUMA_0: 0xb1403000
> TV_H_LUMA_59: 0x0000b060
> TV_H_CHROMA_0: 0xb1403000
> TV_H_CHROMA_59: 0x0000b060
155c155
< MI_ARB_STATE: 0x00000040
---
> MI_ARB_STATE: 0x00000840
157c157
< ECOSKPD: 0x00000306
---
> ECOSKPD: 0x00000307
191,193c191,193
< FENCE 0: 0x00000441 (enabled, X tiled, 8192 pitch,
0x00000000 - 0x01000000 (16384kb))
< FENCE 1: 0x01000400 (disabled)
< FENCE 2: 0x04000431 (enabled, X tiled, 4096 pitch,
0x04000000 - 0x05000000 (16384kb))
---
> FENCE 0: 0x00800241 (enabled, X tiled, 8192 pitch,
0x00800000 - 0x00c00000 (4096kb))
> FENCE 1: 0x00000000 (disabled)
> FENCE 2: 0x00000000 (disabled)
207,209c207,209
< INST_PM: 0x00000100
< pipe A dot 114000 n 2 m1 15 m2 8 p1 2 p2 10
< pipe B dot 119047 n 1 m1 11 m2 8 p1 3 p2 7
---
> INST_PM: 0x00000800
> pipe A dot 160000 n 4 m1 16 m2 8 p1 1 p2 10
> pipe B dot 25170 n 1 m1 11 m2 7 p1 7 p2 14
-------------- next part --------------
sidetft00:/home/display # ./intel_reg_dumper
DCC: 0x000f0400 (single channel, XOR randomization: disabled, XOR bit: 11)
CHDECMISC: 0x22b97420 (XOR bank/rank, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
C0DRB0: 0x000f0400 (0x0400)
C0DRB1: 0x0000000f (0x000f)
C0DRB2: 0x00000000 (0x0000)
C0DRB3: 0x01080000 (0x0000)
C1DRB0: 0x0e0d0d0c (0x0d0c)
C1DRB1: 0x0f0e0e0d (0x0e0d)
C1DRB2: 0x100f0f0e (0x0f0e)
C1DRB3: 0x0e0d100f (0x100f)
C0DRA01: 0x04020108 (0x0108)
C0DRA23: 0x00000402 (0x0402)
C1DRA01: 0x100f0e0d (0x0e0d)
C1DRA23: 0x1211100f (0x100f)
PGETBL_CTL: 0x3ffc0001
VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
VCLK_POST_DIV: 0x01040104 (vga0 p1 = 6, p2 = 2, vga1 p1 = 3, p2 = 2)
DPLL_TEST: 0x00010001 ()
CACHE_MODE_0: 0x00006820
D_STATE: 0x0000000b
DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
RENCLK_GATE_D1: 0x00000000
RENCLK_GATE_D2: 0x00000000
SDVOB: 0xa0480084 (enabled, pipe A, stall enabled, detected)
SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
SDVOUDI: 0x00000000
DSPARB: 0x00002020
DSPFW1: 0x00000000
DSPFW2: 0x00000000
DSPFW3: 0x00000000
ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
LVDS: 0xc020033c (enabled, pipe B, 18 bit, 2 channels)
DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
DVOB: 0xa0480084 (enabled, pipe A, TV stall, -hsync, -vsync)
DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
DVOA_SRCDIM: 0x00000000
DVOB_SRCDIM: 0x00000000
DVOC_SRCDIM: 0x00000000
PP_CONTROL: 0x00000001 (power target: on)
PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
PP_ON_DELAYS: 0x00000000
PP_OFF_DELAYS: 0x00000000
PP_DIVISOR: 0x00270f05
PFIT_CONTROL: 0x00000228
PFIT_PGM_RATIOS: 0x00000000
PORT_HOTPLUG_EN: 0x00000020
PORT_HOTPLUG_STAT: 0x00000b00
DSPACNTR: 0xd8000000 (enabled, pipe A)
DSPASTRIDE: 0x00002000 (8192 bytes)
DSPAPOS: 0x00000000 (0, 0)
DSPASIZE: 0x01df077f (1920, 480)
DSPABASE: 0x00000000
DSPASURF: 0x00000000
DSPATILEOFF: 0x00000000
PIPEACONF: 0x80000000 (enabled, single-wide)
PIPEASRC: 0x077f01df (1920, 480)
PIPEASTAT: 0x00020203 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
PIPEA_GMCH_DATA_M: 0x00000000
PIPEA_GMCH_DATA_N: 0x00000000
PIPEA_DP_LINK_M: 0x00000000
PIPEA_DP_LINK_N: 0x00000000
CURSOR_A_BASE: 0x34eb1000
CURSOR_A_CONTROL: 0x00000000
CURSOR_A_POSITION: 0x8001009f
FPA0: 0x00020f08 (n = 2, m1 = 15, m2 = 8)
FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
DPLL_A: 0xd4020003 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
DPLL_A_MD: 0x00000000
HTOTAL_A: 0x0a9f077f (1920 active, 2720 total)
HBLANK_A: 0x0a9f077f (1920 start, 2720 end)
HSYNC_A: 0x080e07b6 (1975 start, 2063 end)
VTOTAL_A: 0x02a701df (480 active, 680 total)
VBLANK_A: 0x02a701df (480 start, 680 end)
VSYNC_A: 0x01e701e2 (483 start, 488 end)
BCLRPAT_A: 0x00000000
VSYNCSHIFT_A: 0x00000000
DSPBCNTR: 0xd9000000 (enabled, pipe B)
DSPBSTRIDE: 0x00002000 (8192 bytes)
DSPBPOS: 0x00000000 (0, 0)
DSPBSIZE: 0x01df077f (1920, 480)
DSPBBASE: 0x00000000
DSPBSURF: 0x00000000
DSPBTILEOFF: 0x00000000
PIPEBCONF: 0x80000000 (enabled, single-wide)
PIPEBSRC: 0x077f01df (1920, 480)
PIPEBSTAT: 0x00020202 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS)
PIPEB_GMCH_DATA_M: 0x00000000
PIPEB_GMCH_DATA_N: 0x00000000
PIPEB_DP_LINK_M: 0x00000000
PIPEB_DP_LINK_N: 0x00000000
CURSOR_B_BASE: 0x34eb1000
CURSOR_B_CONTROL: 0x00000000
CURSOR_B_POSITION: 0x8001009f
FPB0: 0x00010b08 (n = 1, m1 = 11, m2 = 8)
FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
DPLL_B: 0x99046003 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 7, SDVO mult 1)
DPLL_B_MD: 0x00000000
HTOTAL_B: 0x0a9f077f (1920 active, 2720 total)
HBLANK_B: 0x0a9f077f (1920 start, 2720 end)
HSYNC_B: 0x080e07b6 (1975 start, 2063 end)
VTOTAL_B: 0x02a701df (480 active, 680 total)
VBLANK_B: 0x02a701df (480 start, 680 end)
VSYNC_B: 0x01e701e2 (483 start, 488 end)
BCLRPAT_B: 0x00000000
VSYNCSHIFT_B: 0x00000000
VCLK_DIVISOR_VGA0: 0x00031108
VCLK_DIVISOR_VGA1: 0x00031406
VCLK_POST_DIV: 0x01040104
VGACNTRL: 0x8020008e (disabled)
TV_CTL: 0x10000010
TV_DAC: 0x70000000
TV_CSC_Y: 0x00000000
TV_CSC_Y2: 0x00000000
TV_CSC_U: 0x00000000
TV_CSC_U2: 0x00000000
TV_CSC_V: 0x00000000
TV_CSC_V2: 0x00000000
TV_CLR_KNOBS: 0x00000000
TV_CLR_LEVEL: 0x00000000
TV_H_CTL_1: 0x00000000
TV_H_CTL_2: 0x00000000
TV_H_CTL_3: 0x00000000
TV_V_CTL_1: 0x00000000
TV_V_CTL_2: 0x00000000
TV_V_CTL_3: 0x00000000
TV_V_CTL_4: 0x00000000
TV_V_CTL_5: 0x00000000
TV_V_CTL_6: 0x00000000
TV_V_CTL_7: 0x00000000
TV_SC_CTL_1: 0x00000000
TV_SC_CTL_2: 0x00000000
TV_SC_CTL_3: 0x00000000
TV_WIN_POS: 0x00000000
TV_WIN_SIZE: 0x00000000
TV_FILTER_CTL_1: 0x00000000
TV_FILTER_CTL_2: 0x00000000
TV_FILTER_CTL_3: 0x00000000
TV_CC_CONTROL: 0x00000000
TV_CC_DATA: 0x00000000
TV_H_LUMA_0: 0x00000000
TV_H_LUMA_59: 0x00000000
TV_H_CHROMA_0: 0x00000000
TV_H_CHROMA_59: 0x00000000
FBC_CFB_BASE: 0x00000000
FBC_LL_BASE: 0x00000000
FBC_CONTROL: 0x00000000
FBC_COMMAND: 0x00000000
FBC_STATUS: 0x20000000
FBC_CONTROL2: 0x00000000
FBC_FENCE_OFF: 0x00000000
FBC_MOD_NUM: 0x00000000
MI_MODE: 0x00000200
MI_ARB_STATE: 0x00000040
MI_RDRET_STATE: 0x00000000
ECOSKPD: 0x00000306
DP_B: 0x00000000
DPB_AUX_CH_CTL: 0x00000000
DPB_AUX_CH_DATA1: 0x00000000
DPB_AUX_CH_DATA2: 0x00000000
DPB_AUX_CH_DATA3: 0x00000000
DPB_AUX_CH_DATA4: 0x00000000
DPB_AUX_CH_DATA5: 0x00000000
DP_C: 0x00000000
DPC_AUX_CH_CTL: 0x00000000
DPC_AUX_CH_DATA1: 0x00000000
DPC_AUX_CH_DATA2: 0x00000000
DPC_AUX_CH_DATA3: 0x00000000
DPC_AUX_CH_DATA4: 0x00000000
DPC_AUX_CH_DATA5: 0x00000000
DP_D: 0x00000000
DPD_AUX_CH_CTL: 0x00000000
DPD_AUX_CH_DATA1: 0x00000000
DPD_AUX_CH_DATA2: 0x00000000
DPD_AUX_CH_DATA3: 0x00000000
DPD_AUX_CH_DATA4: 0x00000000
DPD_AUX_CH_DATA5: 0x00000000
AUD_CONFIG: 0x00000000
AUD_HDMIW_STATUS: 0x00000000
AUD_CONV_CHCNT: 0x00000000
VIDEO_DIP_CTL: 0x00000000
AUD_PINW_CNTR: 0x00000000
AUD_CNTL_ST: 0x00000000
AUD_PIN_CAP: 0x00000000
AUD_PINW_CAP: 0x00000000
AUD_PINW_UNSOLRESP: 0x00000000
AUD_OUT_DIG_CNVT: 0x00000000
AUD_OUT_CWCAP: 0x00000000
AUD_GRP_CAP: 0x00000000
FENCE 0: 0x00000441 (enabled, X tiled, 8192 pitch, 0x00000000 - 0x01000000 (16384kb))
FENCE 1: 0x01000400 (disabled)
FENCE 2: 0x04000431 (enabled, X tiled, 4096 pitch, 0x04000000 - 0x05000000 (16384kb))
FENCE 3: 0x00000000 (disabled)
FENCE 4: 0x00000000 (disabled)
FENCE 5: 0x00000000 (disabled)
FENCE 6: 0x00000000 (disabled)
FENCE 7: 0x00000000 (disabled)
FENCE 8: 0x00000000 (disabled)
FENCE 9: 0x00000000 (disabled)
FENCE 10: 0x00000000 (disabled)
FENCE 11: 0x00000000 (disabled)
FENCE 12: 0x00000000 (disabled)
FENCE 13: 0x00000000 (disabled)
FENCE 14: 0x00000000 (disabled)
FENCE 15: 0x00000000 (disabled)
INST_PM: 0x00000100
pipe A dot 114000 n 2 m1 15 m2 8 p1 2 p2 10
pipe B dot 119047 n 1 m1 11 m2 8 p1 3 p2 7
-------------- next part --------------
root at sidetft00:~# ./intel_reg_dumper
DCC: 0x000f0400 (single channel, XOR randomization: disabled, XOR bit: 11)
CHDECMISC: 0x22b97420 (XOR bank/rank, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
C0DRB0: 0x000f0400 (0x0400)
C0DRB1: 0x0000000f (0x000f)
C0DRB2: 0x00000000 (0x0000)
C0DRB3: 0x01080000 (0x0000)
C1DRB0: 0x0e0d0d0c (0x0d0c)
C1DRB1: 0x0f0e0e0d (0x0e0d)
C1DRB2: 0x100f0f0e (0x0f0e)
C1DRB3: 0x0e0d100f (0x100f)
C0DRA01: 0x04020108 (0x0108)
C0DRA23: 0x00000402 (0x0402)
C1DRA01: 0x100f0e0d (0x0e0d)
C1DRA23: 0x1211100f (0x100f)
PGETBL_CTL: 0x3ffc0001
VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
DPLL_TEST: 0x00010001 ()
CACHE_MODE_0: 0x00006820
D_STATE: 0x0000000b
DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
RENCLK_GATE_D1: 0x00000000
RENCLK_GATE_D2: 0x00000000
SDVOB: 0x80480084 (enabled, pipe A, stall disabled, detected)
SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
SDVOUDI: 0x00000000
DSPARB: 0x00001d9c
DSPFW1: 0x00000000
DSPFW2: 0x00000000
DSPFW3: 0x00000000
ADPA: 0x00008c00 (disabled, pipe A, -hsync, -vsync)
LVDS: 0xc0008300 (enabled, pipe B, 18 bit, 1 channel)
DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
DVOB: 0x80480084 (enabled, pipe A, no stall, -hsync, -vsync)
DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
DVOA_SRCDIM: 0x00000000
DVOB_SRCDIM: 0x00000000
DVOC_SRCDIM: 0x00000000
PP_CONTROL: 0x00000001 (power target: on)
PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
PP_ON_DELAYS: 0x025807d0
PP_OFF_DELAYS: 0x01f407d0
PP_DIVISOR: 0x00270f05
PFIT_CONTROL: 0x80000448
PFIT_PGM_RATIOS: 0x00000000
PORT_HOTPLUG_EN: 0x04000220
PORT_HOTPLUG_STAT: 0x00000700
DSPACNTR: 0xd9000000 (enabled, pipe B)
DSPASTRIDE: 0x00002000 (8192 bytes)
DSPAPOS: 0x00000000 (0, 0)
DSPASIZE: 0x01df077f (1920, 480)
DSPABASE: 0x00800000
DSPASURF: 0x00000000
DSPATILEOFF: 0x00000000
PIPEACONF: 0x80000000 (enabled, single-wide)
PIPEASRC: 0x077f01df (1920, 480)
PIPEASTAT: 0x00000000 (status:)
PIPEA_GMCH_DATA_M: 0x00000000
PIPEA_GMCH_DATA_N: 0x00000000
PIPEA_DP_LINK_M: 0x00000000
PIPEA_DP_LINK_N: 0x00000000
CURSOR_A_BASE: 0x00000000
CURSOR_A_CONTROL: 0x00000000
CURSOR_A_POSITION: 0x00000000
FPA0: 0x00041008 (n = 4, m1 = 16, m2 = 8)
FPA1: 0x00041008 (n = 4, m1 = 16, m2 = 8)
DPLL_A: 0xd4010010 (enabled, dvo, default clock, DAC/serial mode, p1 = 1, p2 = 10, SDVO mult 2)
DPLL_A_MD: 0x00000000
HTOTAL_A: 0x066f0555 (1366 active, 1648 total)
HBLANK_A: 0x066f0555 (1366 start, 1648 end)
HSYNC_A: 0x0628059b (1436 start, 1577 end)
VTOTAL_A: 0x032902ff (768 active, 810 total)
VBLANK_A: 0x032902ff (768 start, 810 end)
VSYNC_A: 0x030e0309 (778 start, 783 end)
BCLRPAT_A: 0x00000000
VSYNCSHIFT_A: 0x00000000
DSPBCNTR: 0xd8000000 (enabled, pipe A)
DSPBSTRIDE: 0x00002000 (8192 bytes)
DSPBPOS: 0x00000000 (0, 0)
DSPBSIZE: 0x01df077f (1920, 480)
DSPBBASE: 0x00800000
DSPBSURF: 0x00000000
DSPBTILEOFF: 0x00000000
PIPEBCONF: 0x80000000 (enabled, single-wide)
PIPEBSRC: 0x077f01df (1920, 480)
PIPEBSTAT: 0x00000000 (status:)
PIPEB_GMCH_DATA_M: 0x00000000
PIPEB_GMCH_DATA_N: 0x00000000
PIPEB_DP_LINK_M: 0x00000000
PIPEB_DP_LINK_N: 0x00000000
CURSOR_B_BASE: 0x00000000
CURSOR_B_CONTROL: 0x00000000
CURSOR_B_POSITION: 0x00000000
FPB0: 0x00010b07 (n = 1, m1 = 11, m2 = 7)
FPB1: 0x00010b07 (n = 1, m1 = 11, m2 = 7)
DPLL_B: 0x98406000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 7, p2 = 14, SDVO mult 1)
DPLL_B_MD: 0x00000000
HTOTAL_B: 0x030f027f (640 active, 784 total)
HBLANK_B: 0x030f027f (640 start, 784 end)
HSYNC_B: 0x02e70287 (648 start, 744 end)
VTOTAL_B: 0x01fc009f (160 active, 509 total)
VBLANK_B: 0x015c013f (320 start, 349 end)
VSYNC_B: 0x014f014d (334 start, 336 end)
BCLRPAT_B: 0x00000000
VSYNCSHIFT_B: 0x00000000
VCLK_DIVISOR_VGA0: 0x00031108
VCLK_DIVISOR_VGA1: 0x00031406
VCLK_POST_DIV: 0x00020002
VGACNTRL: 0x80000000 (disabled)
TV_CTL: 0x000c0010
TV_DAC: 0x70000000
TV_CSC_Y: 0x0332012d
TV_CSC_Y2: 0x07d30104
TV_CSC_U: 0x0733052d
TV_CSC_U2: 0x05c70200
TV_CSC_V: 0x0340030c
TV_CSC_V2: 0x06d00200
TV_CLR_KNOBS: 0x00606000
TV_CLR_LEVEL: 0x010b00e1
TV_H_CTL_1: 0x00400359
TV_H_CTL_2: 0x80480022
TV_H_CTL_3: 0x007c0344
TV_V_CTL_1: 0x00f01415
TV_V_CTL_2: 0x00060607
TV_V_CTL_3: 0x80120001
TV_V_CTL_4: 0x000900f0
TV_V_CTL_5: 0x000a00f0
TV_V_CTL_6: 0x000900f0
TV_V_CTL_7: 0x000a00f0
TV_SC_CTL_1: 0xc1710087
TV_SC_CTL_2: 0x6b405140
TV_SC_CTL_3: 0x00000000
TV_WIN_POS: 0x00360024
TV_WIN_SIZE: 0x02640198
TV_FILTER_CTL_1: 0x800010bb
TV_FILTER_CTL_2: 0x00028283
TV_FILTER_CTL_3: 0x00014141
TV_CC_CONTROL: 0x00000000
TV_CC_DATA: 0x00000000
TV_H_LUMA_0: 0xb1403000
TV_H_LUMA_59: 0x0000b060
TV_H_CHROMA_0: 0xb1403000
TV_H_CHROMA_59: 0x0000b060
FBC_CFB_BASE: 0x00000000
FBC_LL_BASE: 0x00000000
FBC_CONTROL: 0x00000000
FBC_COMMAND: 0x00000000
FBC_STATUS: 0x20000000
FBC_CONTROL2: 0x00000000
FBC_FENCE_OFF: 0x00000000
FBC_MOD_NUM: 0x00000000
MI_MODE: 0x00000200
MI_ARB_STATE: 0x00000840
MI_RDRET_STATE: 0x00000000
ECOSKPD: 0x00000307
DP_B: 0x00000000
DPB_AUX_CH_CTL: 0x00000000
DPB_AUX_CH_DATA1: 0x00000000
DPB_AUX_CH_DATA2: 0x00000000
DPB_AUX_CH_DATA3: 0x00000000
DPB_AUX_CH_DATA4: 0x00000000
DPB_AUX_CH_DATA5: 0x00000000
DP_C: 0x00000000
DPC_AUX_CH_CTL: 0x00000000
DPC_AUX_CH_DATA1: 0x00000000
DPC_AUX_CH_DATA2: 0x00000000
DPC_AUX_CH_DATA3: 0x00000000
DPC_AUX_CH_DATA4: 0x00000000
DPC_AUX_CH_DATA5: 0x00000000
DP_D: 0x00000000
DPD_AUX_CH_CTL: 0x00000000
DPD_AUX_CH_DATA1: 0x00000000
DPD_AUX_CH_DATA2: 0x00000000
DPD_AUX_CH_DATA3: 0x00000000
DPD_AUX_CH_DATA4: 0x00000000
DPD_AUX_CH_DATA5: 0x00000000
AUD_CONFIG: 0x00000000
AUD_HDMIW_STATUS: 0x00000000
AUD_CONV_CHCNT: 0x00000000
VIDEO_DIP_CTL: 0x00000000
AUD_PINW_CNTR: 0x00000000
AUD_CNTL_ST: 0x00000000
AUD_PIN_CAP: 0x00000000
AUD_PINW_CAP: 0x00000000
AUD_PINW_UNSOLRESP: 0x00000000
AUD_OUT_DIG_CNVT: 0x00000000
AUD_OUT_CWCAP: 0x00000000
AUD_GRP_CAP: 0x00000000
FENCE 0: 0x00800241 (enabled, X tiled, 8192 pitch, 0x00800000 - 0x00c00000 (4096kb))
FENCE 1: 0x00000000 (disabled)
FENCE 2: 0x00000000 (disabled)
FENCE 3: 0x00000000 (disabled)
FENCE 4: 0x00000000 (disabled)
FENCE 5: 0x00000000 (disabled)
FENCE 6: 0x00000000 (disabled)
FENCE 7: 0x00000000 (disabled)
FENCE 8: 0x00000000 (disabled)
FENCE 9: 0x00000000 (disabled)
FENCE 10: 0x00000000 (disabled)
FENCE 11: 0x00000000 (disabled)
FENCE 12: 0x00000000 (disabled)
FENCE 13: 0x00000000 (disabled)
FENCE 14: 0x00000000 (disabled)
FENCE 15: 0x00000000 (disabled)
INST_PM: 0x00000800
pipe A dot 160000 n 4 m1 16 m2 8 p1 1 p2 10
pipe B dot 25170 n 1 m1 11 m2 7 p1 7 p2 14
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