[Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

[Chris Wilson]

On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky <ben at bwidawsk.net> wrote:
> I think we also want a TLB invalidate here, bit 18.  This requires another
> workaround before issuing this flush: We need 2 Store Data Commands (such as
> MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w/ stall
> (20) and TLB inv bit (18) set

Isn't that workaround itself rather hand-wavy? As in it gives the
hardware sufficient time to complete outstanding writes, but not
necessarily. Or am I thinking of yet another workaround...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre