[Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

[Daniel Vetter]

On Thu, Oct 06, 2011 at 12:36:03AM +0100, Chris Wilson wrote:
> On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky <ben at bwidawsk.net> wrote:
> > I think we also want a TLB invalidate here, bit 18.  This requires another
> > workaround before issuing this flush: We need 2 Store Data Commands (such as
> > MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w/ stall
> > (20) and TLB inv bit (18) set
> 
> Isn't that workaround itself rather hand-wavy? As in it gives the
> hardware sufficient time to complete outstanding writes, but not
> necessarily. Or am I thinking of yet another workaround...

MI_STORE seems to be the hw teams favourite for adding these delays to
paper over hw issues. I've seen it all over bspec ...
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
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