[Intel-gfx] [PATCH 2/2] drm/i915: Force TLB invalidation for erratum on 830/845 BLT

Chris Wilson chris at chris-wilson.co.uk
Mon Apr 16 11:12:30 CEST 2012

On Mon, 16 Apr 2012 11:02:13 +0200, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Mon, Apr 16, 2012 at 09:53:17AM +0100, Chris Wilson wrote:
> > On 830/845, the BLT unit invalidates the wrong PTE in its TLB after the
> > GATT is updated. A simple solution is then to always invalidate the TLB
> > of the BLT prior to each execbuffer.
> > 
> > This does appear to improve the stability slighty, but I am still seeing
> > spurious GPU deaths under memory pressure.
> > 
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=26345
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> In the light of the eventual gpu domain tracking removal, can't we just
> unconditionally set these bit in the new gen2_render_ring_flush function?
> Or is it indeed to expensive?

Of course you can, I have done any measurements to see if any harm is
going to come from extra flushes between batches, as we invariably have
to flush anyway.

Just remember that invalidate+flush 2 step when removing the flush tracking...

Chris Wilson, Intel Open Source Technology Centre

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