In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman at intel.com>
---
lib/Makefile.am | 1 +
lib/intel_chipset.h | 2 +
lib/intel_dpio.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++
lib/intel_gpu_tools.h | 3 ++
lib/intel_reg.h | 13 +++++++
tools/Makefile.am | 2 +
tools/intel_dpio_read.c | 68 +++++++++++++++++++++++++++++++++
tools/intel_dpio_write.c | 67 +++++++++++++++++++++++++++++++++
8 files changed, 250 insertions(+)
create mode 100644 lib/intel_dpio.c
create mode 100644 tools/intel_dpio_read.c
create mode 100644 tools/intel_dpio_write.c
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 88290cb..d8f081f 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -29,6 +29,7 @@ libintel_tools_la_SOURCES = \
rendercopy_gen7.c \
rendercopy.h \
intel_reg_map.c \
+ intel_dpio.c \
$(NULL)
LDADD = $(CAIRO_LIBS)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index a229ea1..9dd4c94 100755
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -196,6 +196,8 @@
dev == PCI_CHIP_IVYBRIDGE_S_GT2 || \
dev == PCI_CHIP_VALLEYVIEW_PO)
+#define IS_VALLEYVIEW(devid) (devid == PCI_CHIP_VALLEYVIEW_PO)
+
#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
devid == PCI_CHIP_HASWELL_M_GT1 || \
devid == PCI_CHIP_HASWELL_S_GT1 || \
diff --git a/lib/intel_dpio.c b/lib/intel_dpio.c
new file mode 100644
index 0000000..acfd201
--- /dev/null
+++ b/lib/intel_dpio.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Vijay Purushothaman <vijay.a.purushothaman at intel.com>
+ *
+ */
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <err.h>
+#include "intel_gpu_tools.h"
+
+static uint32_t intel_display_reg_read(uint32_t reg)
+{
+ struct pci_device *dev = intel_get_pci_device();
+
+ if (IS_VALLEYVIEW(dev->device_id))
+ reg += VLV_DISPLAY_BASE;
+ return (*(volatile uint32_t*)((volatile char*)mmio + reg));
+}
+
+static void intel_display_reg_write(uint32_t reg, uint32_t val)
+{
+ volatile uint32_t *ptr;
+ struct pci_device *dev = intel_get_pci_device();
+
+ if (IS_VALLEYVIEW(dev->device_id))
+ reg += VLV_DISPLAY_BASE;
+ ptr = (volatile uint32_t*)((volatile char*)mmio + reg);
+ *ptr = val;
+}
+
+/*
+ * In SoCs like Valleyview some of the PLL & Lane control registers
+ * can be accessed only through IO side band fabric called DPIO
+ */
+uint32_t
+intel_dpio_reg_read(uint32_t reg)
+{
+ /* Check whether the side band fabric is ready to accept commands */
+ do {
+ usleep(1);
+ } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
+
+ intel_display_reg_write(DPIO_REG, reg);
+ intel_display_reg_write(DPIO_PKT, DPIO_RID |
+ DPIO_OP_READ | DPIO_PORTID | DPIO_BYTE);
+ do {
+ usleep(1);
+ } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
+
+ return intel_display_reg_read(DPIO_DATA);
+}
+
+/*
+ * In SoCs like Valleyview some of the PLL & Lane control registers
+ * can be accessed only through IO side band fabric called DPIO
+ */
+void
+intel_dpio_reg_write(uint32_t reg, uint32_t val)
+{
+ /* Check whether the side band fabric is ready to accept commands */
+ do {
+ usleep(1);
+ } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
+
+ intel_display_reg_write(DPIO_DATA, val);
+ intel_display_reg_write(DPIO_REG, reg);
+ intel_display_reg_write(DPIO_PKT, DPIO_RID |
+ DPIO_OP_WRITE | DPIO_PORTID | DPIO_BYTE);
+ do {
+ usleep(1);
+ } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
+}
diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h
index eb21a16..245d1de 100644
--- a/lib/intel_gpu_tools.h
+++ b/lib/intel_gpu_tools.h
@@ -45,6 +45,9 @@ int intel_register_access_init(struct pci_device *pci_dev, int safe);
void intel_register_access_fini(void);
uint32_t intel_register_read(uint32_t reg);
void intel_register_write(uint32_t reg, uint32_t val);
+/* Following functions are relevant only for SoCs like Valleyview */
+uint32_t intel_dpio_reg_read(uint32_t reg);
+void intel_dpio_reg_write(uint32_t reg, uint32_t val);
#define INTEL_RANGE_RSVD (0<<0) /* Shouldn't be read or written */
#define INTEL_RANGE_READ (1<<0)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index a371d67..ffded64 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -3741,5 +3741,18 @@ typedef enum {
#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
#define SFUSE_STRAP_DDID_DETECTED (1<<0)
+/* Valleyview related items */
+
+/* Valleyview DPIO registers */
+#define VLV_DISPLAY_BASE 0x180000
+#define DPIO_PKT 0x2100
+#define DPIO_RID (0 << 24)
+#define DPIO_OP_WRITE (1 << 16)
+#define DPIO_OP_READ (0 << 16)
+#define DPIO_PORTID (0x12 << 8)
+#define DPIO_BYTE (0xf << 4)
+#define DPIO_BUSY (1 << 0)
+#define DPIO_DATA 0x2104
+#define DPIO_REG 0x2108
#endif /* _I810_REG_H */
diff --git a/tools/Makefile.am b/tools/Makefile.am
index d461f38..71fb087 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -15,6 +15,8 @@ bin_PROGRAMS = \
intel_reg_write \
intel_reg_read \
intel_forcewaked \
+ intel_dpio_read \
+ intel_dpio_write \
intel_l3_parity
noinst_PROGRAMS = \
diff --git a/tools/intel_dpio_read.c b/tools/intel_dpio_read.c
new file mode 100644
index 0000000..c0c904a
--- /dev/null
+++ b/tools/intel_dpio_read.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Vijay Purushothaman <vijay.a.purushothaman at intel.com>
+ *
+ */
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <err.h>
+#include <string.h>
+#include "intel_gpu_tools.h"
+
+static void usage(char *cmdname)
+{
+ printf("Warning : This program will work only on Valleyview\n");
+ printf("Usage: %s [addr]\n", cmdname);
+ printf("\t addr : in 0xXXXX format\n");
+}
+
+int main(int argc, char** argv)
+{
+ int ret = 0;
+ uint32_t reg, val;
+ char *cmdname = strdup(argv[0]);
+ struct pci_device *dev = intel_get_pci_device();
+
+ if (argc != 2 || !IS_VALLEYVIEW(dev->device_id)) {
+ usage(cmdname);
+ ret = 1;
+ goto out;
+ }
+
+ sscanf(argv[1], "0x%x", ®);
+
+ intel_register_access_init(dev, 0);
+
+ val = intel_dpio_reg_read(reg);
+
+ printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val);
+
+ intel_register_access_fini();
+
+out:
+ free(cmdname);
+ return ret;
+}
diff --git a/tools/intel_dpio_write.c b/tools/intel_dpio_write.c
new file mode 100644
index 0000000..f842999
--- /dev/null
+++ b/tools/intel_dpio_write.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Vijay Purushothaman <vijay.a.purushothaman at intel.com>
+ *
+ */
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <err.h>
+#include <string.h>
+#include "intel_gpu_tools.h"
+
+static void usage(char *cmdname)
+{
+ printf("Warning : This program will work only on Valleyview\n");
+ printf("Usage: %s [addr] [val]\n", cmdname);
+ printf("\t addr : in 0xXXXX format\n");
+}
+
+int main(int argc, char** argv)
+{
+ int ret = 0;
+ uint32_t reg, val;
+ char *cmdname = strdup(argv[0]);
+ struct pci_device *dev = intel_get_pci_device();
+
+ if (argc != 3 || !IS_VALLEYVIEW(dev->device_id)) {
+ usage(cmdname);
+ ret = 1;
+ goto out;
+ }
+
+ sscanf(argv[1], "0x%x", ®);
+ sscanf(argv[2], "0x%x", &val);
+
+ intel_register_access_init(dev, 0);
+
+ intel_dpio_reg_write(reg, val);
+
+ intel_register_access_fini();
+
+out:
+ free(cmdname);
+ return ret;
+}
--
1.7.9.5