[Intel-gfx] [PATCH] drm/i915: Use the correct size of the GTT for placing the per-process entries

[Ben Widawsky]

On 2012-08-24 01:12, Chris Wilson wrote:
> The current layout is to place the per-process tables at the end of 
> the
> GTT. However, this is currently using a hardcoded maximum size for 
> the GTT
> and not taking in account limitations imposed by the BIOS. Use the 
> value
> for the total number of entries allocated in the table as provided by
> the configuration registers.
>
> Reported-by: Matthew Garrett <mjg at redhat.com>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
> Cc: Ben Widawsky <ben at bwidawsk.net>
> Cc: Matthew Garret <mjg at redhat.com>

details... Can someone remind me why we didn't put it at the bottom?
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 528fd43..4c03544 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -72,7 +72,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device 
> *dev)
>  	/* ppgtt PDEs reside in the global gtt pagetable, which has 
> 512*1024
>  	 * entries. For aliasing ppgtt support we just steal them at the 
> end for
>  	 * now. */
> -	first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;
> +	first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries -
> I915_PPGTT_PD_ENTRIES;
>
>  	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
>  	if (!ppgtt)

-- 
Ben Widawsky, Intel Open Source Technology Center