[Intel-gfx] [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>

On Fri, Dec 14, 2012 at 8:38 PM, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> Quoting from Bspec, 3D_CHICKEN1, bit 10
>
> This bit needs to be set always to "1", Project: DevSNB "
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  drivers/gpu/drm/i915/intel_pm.c |    4 ++++
>  2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f834804..d72744e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -518,6 +518,7 @@
>   * the enables for writing to the corresponding low bit.
>   */
>  #define _3D_CHICKEN    0x02084
> +#define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB     (1 << 10)
>  #define _3D_CHICKEN2   0x0208c
>  /* Disables pipelining of read flushes past the SF-WIZ interface.
>   * Required on all Ironlake steppings according to the B-Spec, but the
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index abfff29..2fddd17 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3474,6 +3474,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>                    I915_READ(ILK_DISPLAY_CHICKEN2) |
>                    ILK_ELPIN_409_SELECT);
>
> +       /* WaDisableHiZPlanesWhenMSAAEnabled */
> +       I915_WRITE(_3D_CHICKEN,
> +                  _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
> +
>         I915_WRITE(WM3_LP_ILK, 0);
>         I915_WRITE(WM2_LP_ILK, 0);
>         I915_WRITE(WM1_LP_ILK, 0);
> --
> 1.7.10.4
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br