[Intel-gfx] [PATCH] drm/modes: do not enforce an odd vtotal for interlaced modes

Adam Jackson ajax at redhat.com
Mon Feb 6 19:22:25 CET 2012

On 2/3/12 4:37 AM, Dave Airlie wrote:
> On Fri, Jan 27, 2012 at 9:40 PM, Daniel Vetter<daniel.vetter at ffwll.ch>  wrote:
>> CEA actually specifies an interlaced mode with even vtotal and
>> supplies a diagram showing how this is supposed to work.
>> Note that interlaced modes with an even vtotal seem to be a fairly
>> recent invention. All modelines lore I could dig up with googling says
>> that vtotal for interlaced modes _needs_ to be odd. But the even
>> modelines in CEA are not a spec-bug, there's a figure in CEA-861-E
>> called "Figure 5 Special Interlaced Video Format Timing (Even Vtotal)"
>> that explains how it's supposed to work. Furthermore intel Bspec
>> explicitly mentions that both odd and even interlaced vtotal are
>> supported (VTOTAL register in the south display engine of PCH split
>> chips).
>> Cc: Adam Jackson<ajax at redhat.com>
>> Signed-Off-by: Daniel Vetter<daniel.vetter at ffwll.ch>
>> ---
> Ajax? I'd like your ack/review on this.

That |= 1 logic was just slavishy copied from the server's RANDR code, 
which afaict slavishly copied it from xfree86 4, and I think even that 
was copypasta from xfree86 3.  I don't know what it was ever meant to do.

- ajax

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