[Intel-gfx] [PATCH 05/14] drm/i915: kill ranged cpu read domain support

Daniel Vetter daniel at ffwll.ch
Thu Feb 16 18:38:08 CET 2012

On Thu, Feb 16, 2012 at 08:48:07AM -0800, Eric Anholt wrote:
> On Thu, 16 Feb 2012 13:11:31 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> > No longer needed.
> What this code was for: Before gtt mapping, we were doing software
> fallbacks in Mesa with pread/write on pages at a time (or worse) of the
> framebuffer.  It would regularly result in hitting the same page again,
> since I was only caching the last page I'd pulled out, instead of
> keeping a whole copy of the framebuffer during the fallback.

Urgh, that's not really efficient ;-) I think for s/w fallbacks and
readbacks we can presume decent damage tracking (like sna does) on the
userspace sides.

> Since we've been doing gtt mapping for years at this point, I'm happy to
> see the code die.
> I'm not sure about the rest of the code.  In particular, for the code
> that's switching between gtt and cpu mappings to handle a read/write,
> I'm concerned about whether the behavior matches for tiled objects.  I
> haven't reviewed enough to be sure.

Behaviour should match old code if you read/write entire pages (we should
have decent set of tests for that). If you do non-cacheline-aligned
reads/writes on tiled objects, we might hit an issue, but they should be
solveable (I've simply been too lazy to write testcases for this). Not
cacheline aligned reads/writes on untiled also work, I've created a set of
tests to exercise issues there (and tested the tests by omitting some of
the clflushes, i.e. all the clfushes now left _are_ required).

If old mesa depends on sub-page reads/writes to tiled objects I need to
create the respective tests and double-check the code, otherwise I think
we're covered. Do you want me to adapt the tests to check correctness for
sub-page reads/writes to tiled objects?

Thanks, Daniel
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48

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