[Intel-gfx] [PATCH 2/4] intel: Add decode for gen7 3DSTATE_WM.

[Daniel Vetter]

On Mon, Feb 20, 2012 at 09:55:35AM -0800, Eric Anholt wrote:
> This requires pulling the gen6 3DSTATE_WM out to a function so it
> doesn't override gen7's handler.
> ---
>  intel/intel_decode.c              |  178 ++++++++++++++++++++++++++++---------
>  intel/tests/gen7-3d.batch-ref.txt |   70 +++------------
>  2 files changed, 150 insertions(+), 98 deletions(-)
> 
> diff --git a/intel/intel_decode.c b/intel/intel_decode.c
> index 00908d0..02e81f9 100644
> --- a/intel/intel_decode.c
> +++ b/intel/intel_decode.c
> @@ -2859,6 +2859,140 @@ gen7_3DSTATE_CONSTANT_HS(struct drm_intel_decode *ctx)
>  	return gen7_3DSTATE_CONSTANT(ctx, "HS");
>  }
>  
> +
> +static int
> +gen6_3DSTATE_WM(struct drm_intel_decode *ctx)
> +{
> +	instr_out(ctx, 0, "3DSTATE_WM\n");
> +	instr_out(ctx, 1, "kernel start pointer 0\n");
> +	instr_out(ctx, 2,
> +		  "SPF=%d, VME=%d, Sampler Count %d, "
> +		  "Binding table count %d\n",
> +		  (ctx->data[2] >> 31) & 1,
> +		  (ctx->data[2] >> 30) & 1,
> +		  (ctx->data[2] >> 27) & 7,
> +		  (ctx->data[2] >> 18) & 0xff);
> +	instr_out(ctx, 3, "scratch offset\n");
> +	instr_out(ctx, 4,
> +		  "Depth Clear %d, Depth Resolve %d, HiZ Resolve %d, "
> +		  "Dispatch GRF start[0] %d, start[1] %d, start[2] %d\n",
> +		  (ctx->data[4] & (1 << 30)) != 0,
> +		  (ctx->data[4] & (1 << 28)) != 0,
> +		  (ctx->data[4] & (1 << 27)) != 0,
> +		  (ctx->data[4] >> 16) & 0x7f,
> +		  (ctx->data[4] >> 8) & 0x7f,
> +		  (ctx->data[4] & 0x7f));
> +	instr_out(ctx, 5,
> +		  "MaxThreads %d, PS KillPixel %d, PS computed Z %d, "
> +		  "PS use sourceZ %d, Thread Dispatch %d, PS use sourceW %d, "
> +		  "Dispatch32 %d, Dispatch16 %d, Dispatch8 %d\n",
> +		  ((ctx->data[5] >> 25) & 0x7f) + 1,
> +		  (ctx->data[5] & (1 << 22)) != 0,
> +		  (ctx->data[5] & (1 << 21)) != 0,
> +		  (ctx->data[5] & (1 << 20)) != 0,
> +		  (ctx->data[5] & (1 << 19)) != 0,
> +		  (ctx->data[5] & (1 << 8)) != 0,
> +		  (ctx->data[5] & (1 << 2)) != 0,
> +		  (ctx->data[5] & (1 << 1)) != 0,
> +		  (ctx->data[5] & (1 << 0)) != 0);
> +	instr_out(ctx, 6,
> +		  "Num SF output %d, Pos XY offset %d, ZW interp mode %d , "
> +		  "Barycentric interp mode 0x%x, Point raster rule %d, "
> +		  "Multisample mode %d, "
> +		  "Multisample Dispatch mode %d\n",
> +		  (ctx->data[6] >> 20) & 0x3f,
> +		  (ctx->data[6] >> 18) & 3,
> +		  (ctx->data[6] >> 16) & 3,
> +		  (ctx->data[6] >> 10) & 0x3f,
> +		  (ctx->data[6] & (1 << 9)) != 0,
> +		  (ctx->data[6] >> 1) & 3,
> +		  (ctx->data[6] & 1));
> +	instr_out(ctx, 7, "kernel start pointer 1\n");
> +	instr_out(ctx, 8, "kernel start pointer 2\n");
> +
> +	return 9;
> +}
> +
> +static int
> +gen7_3DSTATE_WM(struct drm_intel_decode *ctx)
> +{
> +	const char *computed_depth = "";
> +	const char *early_depth = "";
> +	const char *zw_interp = "";
> +
> +	switch ((ctx->data[1] >> 23) & 0x3) {
> +	case 0:
> +		computed_depth = "";
> +		break;
> +	case 1:
> +		computed_depth = "computed depth";
> +		break;
> +	case 2:
> +		computed_depth = "computed depth >=";
> +		break;
> +	case 3:
> +		computed_depth = "computed depth <=";
> +		break;
> +	}
> +
> +	switch ((ctx->data[1] >> 21) & 0x3) {
> +	case 0:
> +		early_depth = "";
> +		break;
> +	case 1:
> +		early_depth = ", EDSC_PSEXEC";
> +		break;
> +	case 2:
> +		early_depth = ", EDSC_PREPS";
> +		break;
> +	case 3:
> +		early_depth = ", BAD EDSC";
> +		break;
> +	}
> +
> +	switch ((ctx->data[1] >> 21) & 0x3) {

Afacs this should be >> 17 instead of >> 21. With that fixed patches 1-3
are Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch> and patch 4 is
Acked-by: Daniel Vetter <daniel.vetter at ffwll.ch>
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48