[Intel-gfx] [PATCH] drm/i915: enable MI_WTF bit; I mean MI_FLUSH

Daniel Vetter daniel at ffwll.ch
Thu Jan 19 11:35:22 CET 2012

On Wed, Jan 18, 2012 at 08:52:42PM -0800, Ben Widawsky wrote:
> We've seen a few patches now which switch the flush enable bit from bit
> 11 to bit 12 (as the documentation suggests it should be). However this
> turned out to be problematic for us.
> The simulator has shed some light for us. It's not bit 11, and it's not
> bit 12; it's both. Instead of renaming the bits according to the docs
> since we're still really not sure, I've decided to just make the
> MI_FLUSH_ENABLE be both bits. As an aside, the simulator still makes a
> distinction for these two bits, however the error message doesn't seem
> to.
> I don't believe this is actually required for the simulator to be
> function, but it does produce an annoying error message every time
> MI_FLUSH is used without this.
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>

Because HAS seems to only be able to run ivb fulsim: Have you checked snb
fulsim source for this warning and it's also there? Your changelog is also
silent on how well this works on real hw, can you clarify?

Last but not least, please add a small comment to the #define explaining
what's going on.

Cheers, Daniel
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48

More information about the Intel-gfx mailing list