[Intel-gfx] [PATCH 1/8] drm/i915: clean up interlaced pipeconf bit definitions

[Eugeni Dodonov]

On Sat, Jan 28, 2012 at 11:49, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:

> +#define   PIPECONF_PROGRESSIVE                 (0 << 21)
> +#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL        (4 << 21) /* gen4
> only */
> +#define   PIPECONF_INTERLACE_W_SYNC_SHIFT      (5 << 21) /* gen4 only */
> +#define   PIPECONF_INTERLACE_W_FIELD_INDICATION        (6 << 21)
> +#define   PIPECONF_INTERLACE_FIELD_0_ONLY      (7 << 21) /* gen3 only */
>

<bikeshedding>
As you are touching this code, perhaps you could align the
tabification/spacing as well?
</bikeshedding>

Other than that,
Reviewed-by: Eugeni Dodonov <eugeni.dodonov at intel.com>

-- 
Eugeni Dodonov
 <http://eugeni.dodonov.net/>
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