[Intel-gfx] [PATCH 2/2] drm/i915: adjust framebuffer base address on gen4+

[Chris Wilson]

On Thu,  5 Jul 2012 12:17:30 +0200, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> The tileoffset register only supports a limited offset in x/y of 4096,
> so for giant screen configuration with a shared fb we wrap around.
> 
> Fix this by computing a linear offset in tiles (pages) and only use
> the tileoffset register to offset within the tile.

One thing I did spot after hitting send, is that we don't enforce that
the new_fb has the same pitch as the old_fb when flipping. Whilst there
are patching floating around to do so in the midlayer, we need to
express that constraint now for this patch to be valid.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre