[Intel-gfx] [PATCH 2/2] drm/i915: adjust framebuffer base address on gen4+

[Daniel Vetter]

On Thu, Jul 05, 2012 at 11:29:10AM +0100, Chris Wilson wrote:
> On Thu,  5 Jul 2012 12:17:30 +0200, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> > The tileoffset register only supports a limited offset in x/y of 4096,
> > so for giant screen configuration with a shared fb we wrap around.
> > 
> > Fix this by computing a linear offset in tiles (pages) and only use
> > the tileoffset register to offset within the tile.
> > 
> > Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> Both Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

Thanks for the review, I've addressed your pitch concern from the other
mail by merging one of Ville's patches.

> We could do with validating that the CRTC is within the fb->obj,
> otherwise we run foul of hanging the hardware. (Since this is a
> pre-existing condition it doesn't mar these patches.)
> 
> So the only question is whether we indicate to userspace that the kernel
> is fixed? Or just kill the w/a in userspace and for reasons of sanity
> strongly encourage everyone who hits this to upgrade? Since this is no
> stable material, having keeping the w/a seems to make sense...

As discussed I think we'll just ask ppl to upgrade their kernel and should
rip out the hack in userspace ...
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48