[Intel-gfx] [PATCH 3/6] drm/i915: Remove the per-ring write list

[Chris Wilson]

On Fri, 13 Jul 2012 09:49:48 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> No. Because by the time the previous breadcrumb has been seen we are
> guarranteed to have flushed the gpu caches. So any wait in the future we
> have flushed the caches before returning.

Egg on face time.

The issue is on the waiter side, since we don't wait unless
pending_gpu_write is set. Tracking the last write seqno seems safest
when removing the gpu_write_list.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre