[Intel-gfx] [PATCH 3/6] drm/i915: Remove the per-ring write list

[Daniel Vetter]

On Fri, Jul 13, 2012 at 09:53:33AM +0100, Chris Wilson wrote:
> On Fri, 13 Jul 2012 09:49:48 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > No. Because by the time the previous breadcrumb has been seen we are
> > guarranteed to have flushed the gpu caches. So any wait in the future we
> > have flushed the caches before returning.
> 
> Egg on face time.
> 
> The issue is on the waiter side, since we don't wait unless
> pending_gpu_write is set. Tracking the last write seqno seems safest
> when removing the gpu_write_list.

Imo tracking the last write seqno would be an extension (i.e. separate
patch), the current code that just tracks pending_gpu_write should work
(and if I haven't botched up the i-g-t tests, it should be able to catch
that kind of stuff).
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
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