[Intel-gfx] [PATCH 1/2] drm/i915: fix color order for BGR formats on SNB

Jesse Barnes jbarnes at virtuousgeek.org
Wed Mar 7 16:02:02 CET 2012


Dave, not sure if Keith has setup his -fixes tree again, but this one
needs to go to Linus in your next pull assuming you're doing one.

Otherwise we can just send it to stable after 3.3 is out.

I have one more similar fix for the i915 fb init code that was
preventing us from using BGR formats (a fuller fix to make per-chipset
format lists for display and sprite can wait until -next).  I'll send
that after some testing today.

Thanks,
Jesse

On Mon, 27 Feb 2012 12:40:10 -0800
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> Had the wrong bits and field definitions.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     |    2 +-
>  drivers/gpu/drm/i915/intel_sprite.c |    6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 03c53fc..558ac71 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2689,7 +2689,7 @@
>  #define   DVS_FORMAT_RGBX888	(2<<25)
>  #define   DVS_FORMAT_RGBX161616	(3<<25)
>  #define   DVS_SOURCE_KEY	(1<<22)
> -#define   DVS_RGB_ORDER_RGBX	(1<<20)
> +#define   DVS_RGB_ORDER_XBGR	(1<<20)
>  #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
>  #define   DVS_YUV_ORDER_YUYV	(0<<16)
>  #define   DVS_YUV_ORDER_UYVY	(1<<16)
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c index 2288abf..a083504 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -225,16 +225,16 @@ snb_update_plane(struct drm_plane *plane,
> struct drm_framebuffer *fb, 
>  	/* Mask out pixel format bits in case we change it */
>  	dvscntr &= ~DVS_PIXFORMAT_MASK;
> -	dvscntr &= ~DVS_RGB_ORDER_RGBX;
> +	dvscntr &= ~DVS_RGB_ORDER_XBGR;
>  	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
>  
>  	switch (fb->pixel_format) {
>  	case DRM_FORMAT_XBGR8888:
> -		dvscntr |= DVS_FORMAT_RGBX888;
> +		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
>  		pixel_size = 4;
>  		break;
>  	case DRM_FORMAT_XRGB8888:
> -		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_RGBX;
> +		dvscntr |= DVS_FORMAT_RGBX888;
>  		pixel_size = 4;
>  		break;
>  	case DRM_FORMAT_YUYV:




More information about the Intel-gfx mailing list