[Intel-gfx] [PATCH] drm/i915: IVB missed irqs w/a

[Ben Widawsky]

Request for testing.

This is the proposed workaround from the HW team for the missed IRQ
issue. I do not have a machine to test on, so it's just compile tested.
This is very similar to another workaround I implemented, but I never
tried it on IVB, and don't recall if I ever mailed those out.

Anyone who is capable of testing this, please undo the previous
workaround, and try this patch.

Meanwhile, I'll try to find a similar workaround for SNB.

Thanks.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_irq.c |   15 +++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h |    4 ++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4c89149..0deae71 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -479,11 +479,26 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 
 	atomic_inc(&dev_priv->irq_received);
 
+again:
+	/* Clear out message status bits */
+	I915_WRITE(GEN7_CPU_MSG_SENT_STATUS, 0xFFFFFFFF);
+	I915_WRITE(GEN7_CPU_MSG_RCVD_STATUS1, 0xFFFFFFFF);
+	I915_WRITE(GEN7_CPU_MSG_RCVD_STATUS2, 0xFFFFFFFF);
+	POSTING_READ(GEN7_CPU_MSG_SENT_STATUS);
+
 	/* disable master interrupt before clearing iir  */
 	de_ier = I915_READ(DEIER);
 	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 	POSTING_READ(DEIER);
 
+	/* Check if any render response activity occurred */
+	if ((I915_READ(GEN7_CPU_MSG_RCVD_STATUS1) & 0xfff1c) ||
+	    (I915_READ(GEN7_CPU_MSG_RCVD_STATUS2) & 0x7e00)) {
+		I915_WRITE(DEIER, de_ier | DE_MASTER_IRQ_CONTROL);
+		POSTING_READ(DEIER);
+		goto again;
+	}
+
 	de_iir = I915_READ(DEIIR);
 	gt_iir = I915_READ(GTIIR);
 	pch_iir = I915_READ(SDEIIR);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..181f2af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3776,6 +3776,10 @@
 #define GEN6_RC6pp_THRESHOLD			0xA0C0
 #define GEN6_PMINTRMSK				0xA168
 
+#define GEN7_CPU_MSG_SENT_STATUS		0x42030
+#define GEN7_CPU_MSG_RCVD_STATUS1		0x42034
+#define GEN7_CPU_MSG_RCVD_STATUS2		0x42038
+
 #define GEN6_PMISR				0x44020
 #define GEN6_PMIMR				0x44024 /* rps_lock */
 #define GEN6_PMIIR				0x44028
-- 
1.7.9.4