[Intel-gfx] [RFC] [PATCH 00/38] Haswell

Eugeni Dodonov eugeni.dodonov at intel.com
Thu Mar 22 02:09:35 CET 2012

Hi folks,

To contribute to everyones curiosity and further enrich Phoronix articles
:), this is the initial Haswell enablement patchset for basic modesetting
support over VGA.

This is actually the first time I am doing such enablement, and the
combination of HSW/LPT changes proved to be quite tricky, yet also very cool
to do. But certainly, while I tried to split the patches in the best way to
'tell a story', I suspect lots and lots of things could be improved. So
bikeshedding is much welcomed! And of course, there are still a bunch of
things missing, but those can be done in parallel now.

As for those patches, I organized them in the following way:
 - The first part adds new hardware information and new registers which we'll
   need to make it work (a.k.a, 'The Pledge'). This goes from patch 01 until
   patch 21.
 - The second part does small changes to existent functions to make them work
   on Haswell ('The Turn'). This goes from patch 22 to patch 28.  Haswell is
   not quite Gen7, but is shares lots of stuff with what we already have, so
   there was no point in reinventing the wheel just now.
 - The third part makes things work by enabling power wells, DDI and FDI
   connections, PCH-specific stuff and so on ('The Prestige'). This is from
   patch 29 to patch 35. Those are the scariest ones, but I couldn't split them
   better and still maintain logical consistency among them.  Initially, those
   were 24 small patches, but it was very hard to keep track of them, so I
   combined them into just 6 for this patchset.
 - And finally, there are 2 last patches ('The Prestige Debug' :)) which won't
   be present in the final series, but are helpful at least for me to trace
   where things go wrong. So if you run into issues and want to send me a
   dmesg, those traces will make my life so much easier.

I didn't wanted to go much deeper with HSW for now because I would end up
doing a massive code reordering to maintain my mental sanity, and as we
already discussed by email earlier today Jesse is running into same problems
as well. So perhaps we should just settle on doing some cleanup in our
intel_display module before adding more platform-specific stuff?

And finally, I'd like to thank once again Jesse with his help on some of the
trickiest issues, and Ben for taking a look at those patches and point me at
things I've been doing wrong :).


Eugeni Dodonov (37):
  drm/i915: add Haswell devices and their PCI IDs
  drm/i915: add support for LynxPoint PCH
  drm/i915: add HAS_PLL_SPLIT macro
  drm/i915: add haswell into the PCH SPLIT company
  drm/i915: add support for power wells
  drm/i915: add DDI registers
  drm/i915: add DP_TP_CTL registers
  drm/i915: add DP_TP_STATUS registers
  drm/i915: add definitions for DDI_BUF_CTL registers
  drm/i915: add definition of LPT FDI port width registers
  drm/i915: add definition of DDI buffer translations regs
  drm/i915: add SBI registers
  drm/i915: add support for SBI ops
  drm/i915: add PIXCLK_GATE register
  drm/i915: add S PLL control
  drm/i915: add port clock selection support for HSW
  drm/i915: add SSC offsets for SBI access
  drm/i915: add GTC registers
  drm/i915: add LCPLL control registers
  drm/i915: add WM_LINETIME registers
  drm/i915: calculate watermarks on Gen7 archs in one place
  drm/i915: program WM_LINETIME on Haswell
  drm/i915: do not set 6BPP dithering on haswell
  drm/i915: share forcewaking code between IVB and HSW
  drm/i915: haswell has 3 pipes as well
  drm/i915: reuse Ivybridge interrupts code for Haswell
  drm/i915: share pipe count handling with Ivybridge
  drm/i915: share IVB cursor routine with Haswell
  drm/i915: enable power wells on haswell init
  drm/i915: disable rc6 on haswell for now
  drm/i915: enable PCH earlier
  drm/i915: perform Haswell DDI link training in FDI mode
  drm/i915: double-write DDI translation table
  drm/i915: do not use fdi_normal_train on haswell
  drm/i915: program iCLKIP on Lynx Point
  drm/i915: add warning when using old bits on Haswell/LPT
  drm/i915: dump registers read/write ops

 drivers/char/agp/intel-agp.c         |    4 +
 drivers/char/agp/intel-agp.h         |   11 +
 drivers/char/agp/intel-gtt.c         |   14 +
 drivers/gpu/drm/i915/i915_dma.c      |    2 +-
 drivers/gpu/drm/i915/i915_drv.c      |   29 ++
 drivers/gpu/drm/i915/i915_drv.h      |    7 +-
 drivers/gpu/drm/i915/i915_irq.c      |    6 +-
 drivers/gpu/drm/i915/i915_reg.h      |  181 ++++++++++
 drivers/gpu/drm/i915/intel_display.c |  656 ++++++++++++++++++++++++++++++++--
 9 files changed, 883 insertions(+), 27 deletions(-)


More information about the Intel-gfx mailing list