[Intel-gfx] [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:58PM -0300, Eugeni Dodonov wrote:
> We don't have those bits on Haswell anymore, so do not set them.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>

Hm, how is 6bpp dithering supposed to work now, when e.g. a lame dp link
can't handle more due to bandwidth issues?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |    5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e056c32..24a0a6c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5335,9 +5335,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
>  	if (is_dp) {
>  		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
> -			pipeconf |= PIPECONF_BPP_6 |
> -				    PIPECONF_DITHER_EN |
> +			pipeconf |= PIPECONF_DITHER_EN |
>  				    PIPECONF_DITHER_TYPE_SP;
> +			if (!IS_HASWELL(dev))
> +				pipeconf |= PIPECONF_BPP_6;
>  		}
>  	}
>  
> -- 
> 1.7.9.2
> 
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-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48