[Intel-gfx] [PATCH 07/37] drm/i915: add DP_TP_CTL registers
Chris Wilson
chris at chris-wilson.co.uk
Thu Mar 22 11:43:57 CET 2012
On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov <eugeni.dodonov at intel.com> wrote:
> This is one set of those registers for each pipe.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 09b2267..7a9232e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3890,4 +3890,20 @@
> #define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
> #define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
>
> +/* DisplayPort Transport Control */
> +#define DP_TP_CTL_A 0x64040
> +#define DP_TP_CTL_B 0x64140
> +#define DP_TP_CTL_C 0x64240
> +#define DP_TP_CTL_D 0x64340
> +#define DP_TP_CTL_E 0x64440
> +#define DP_TP_CTL_ENABLE (1<<31)
> +#define DP_TP_CTL_MODE_SST (0<<27)
> +#define DP_TP_CTL_MODE_MST (1<<27)
> +#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
> +#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
> +#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
> +#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
> +#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
> +#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Would these not benefit from a #define DP_TP_CTL(pipe)?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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