[Intel-gfx] [PATCH 10/25] drm/i915: Enable DP panel power sequencing for ValleyView

Ben Widawsky ben at bwidawsk.net
Thu Mar 22 19:31:05 CET 2012

On Wed, 21 Mar 2012 12:48:31 -0700
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> VLV supports two dp panels, there are two set of panel power sequence
> registers which needed to be programmed based on the configured
> pipe. This patch add supports for the same
> Signed-off-by: Beeresh G <beeresh.g at intel.com>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman at intel.com>
> Reviewed-by: Jesse Barnes <jesse.barnes at intel.com>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Acked-by: Ben Widawsky <ben at bwidawsk.net>

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