[Intel-gfx] [PATCH 08/26] drm/i915: add DPIO read/write functions for ValleyView
Ben Widawsky
ben at bwidawsk.net
Fri Mar 23 05:03:46 CET 2012
On Thu, Mar 22, 2012 at 02:38:50PM -0700, Jesse Barnes wrote:
> ValleyView and similar hardware (like CedarView) put some display
> related registers like the PLL controls and dividers on a DPIO bus. Add
> simple indirect register access routines to get to those registers.
>
> v2: move new wait_for macro to intel_drv.h (Ben)
> fix DPIO_PKT double write (Ben)
> add debugfs file
>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 48 ++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 4 ++
> drivers/gpu/drm/i915/i915_reg.h | 55 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 61 ++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 14 ++++++++
> 5 files changed, 182 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fdb7cce..5693de1 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1502,6 +1502,53 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
> return 0;
> }
>
> +static int i915_dpio_info(struct seq_file *m, void *data)
> +{
> + struct drm_info_node *node = (struct drm_info_node *) m->private;
> + struct drm_device *dev = node->minor->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int ret;
> +
> +
> + ret = mutex_lock_interruptible(&dev->mode_config.mutex);
> + if (ret)
> + return ret;
> +
> + if (!IS_VALLEYVIEW(dev)) {
> + seq_printf(m, "unsupported\n");
> + return 0;
> + }
Chris already caught this bug. and I see it fixed in your repo.
> +
> + seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
> +
> + seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
> + intel_dpio_read(dev_priv, _DPIO_DIV_A));
> + seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
> + intel_dpio_read(dev_priv, _DPIO_DIV_B));
> +
> + seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
> + intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
> + seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
> + intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
> +
> + seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
> + intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
> + seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
> + intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
> +
> + seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
> + intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
> + seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
> + intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
> +
> + seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
> + intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
> +
> + mutex_unlock(&dev->mode_config.mutex);
> +
> + return 0;
> +}
> +
> static int
> i915_debugfs_common_open(struct inode *inode,
> struct file *filp)
> @@ -1844,6 +1891,7 @@ static struct drm_info_list i915_debugfs_list[] = {
> {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
> {"i915_swizzle_info", i915_swizzle_info, 0},
> {"i915_ppgtt_info", i915_ppgtt_info, 0},
> + {"i915_dpio", i915_dpio_info, 0},
> };
> #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cacc8d3..2b8b32d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -355,6 +355,10 @@ typedef struct drm_i915_private {
>
> /* protects the irq masks */
> spinlock_t irq_lock;
> +
> + /* DPIO indirect register protection */
> + spinlock_t dpio_lock;
> +
> /** Cached value of IMR to avoid reads in updating the bitfield */
> u32 pipestat[2];
> u32 irq_mask;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 86de215..749e390 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -301,6 +301,61 @@
> #define DEBUG_RESET_RENDER (1<<8)
> #define DEBUG_RESET_DISPLAY (1<<9)
>
> +/*
> + * DPIO - a special bus for various display related registers to hide behind:
> + * 0x800c: m1, m2, n, p1, p2, k dividers
> + * 0x8014: REF and SFR select
> + * 0x8014: N divider, VCO select
> + * 0x801c/3c: core clock bits
> + * 0x8048/68: low pass filter coefficients
> + * 0x8100: fast clock controls
> + */
> +#define DPIO_PKT 0x2100
> +#define DPIO_RID (0<<24)
> +#define DPIO_OP_WRITE (1<<16)
> +#define DPIO_OP_READ (0<<16)
> +#define DPIO_PORTID (0x12<<8)
> +#define DPIO_BYTE (0xf<<4)
> +#define DPIO_BUSY (1<<0) /* status only */
> +#define DPIO_DATA 0x2104
> +#define DPIO_REG 0x2108
> +#define DPIO_CTL 0x2110
> +#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
> +#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
> +#define DPIO_SFR_BYPASS (1<<1)
> +#define DPIO_RESET (1<<0)
> +
> +#define _DPIO_DIV_A 0x800c
> +#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
> +#define DPIO_K_SHIFT (24) /* 4 bits */
> +#define DPIO_P1_SHIFT (21) /* 3 bits */
> +#define DPIO_P2_SHIFT (16) /* 5 bits */
> +#define DPIO_N_SHIFT (12) /* 4 bits */
> +#define DPIO_ENABLE_CALIBRATION (1<<11)
> +#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
> +#define DPIO_M2DIV_MASK 0xff
> +#define _DPIO_DIV_B 0x802c
> +#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
> +
> +#define _DPIO_REFSFR_A 0x8014
> +#define DPIO_REFSEL_OVERRIDE 27
> +#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
> +#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
> +#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
> +#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
> +#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
> +#define _DPIO_REFSFR_B 0x8034
> +#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
> +
> +#define _DPIO_CORE_CLK_A 0x801c
> +#define _DPIO_CORE_CLK_B 0x803c
> +#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
> +
> +#define _DPIO_LFP_COEFF_A 0x8048
> +#define _DPIO_LFP_COEFF_B 0x8068
> +#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
> +
> +#define DPIO_FASTCLK_DISABLE 0x8100
>
> /*
> * Fence registers
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 22619c6..f27728c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -360,6 +360,64 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
> .find_pll = intel_find_pll_ironlake_dp,
> };
>
> +u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
> +{
> + unsigned long flags;
> + u32 val = 0;
> +
> + spin_lock_irqsave(&dev_priv->dpio_lock, flags);
> + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> + DRM_ERROR("DPIO idle wait timed out\n");
> + goto out_unlock;
> + }
> +
> + I915_WRITE(DPIO_REG, reg);
> + I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
> + DPIO_BYTE);
> + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> + DRM_ERROR("DPIO read wait timed out\n");
> + goto out_unlock;
> + }
> + val = I915_READ(DPIO_DATA);
> +
> +out_unlock:
> + spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
> + return val;
> +}
> +
> +static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> + u32 val)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dev_priv->dpio_lock, flags);
> + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> + DRM_ERROR("DPIO idle wait timed out\n");
> + goto out_unlock;
> + }
> +
> + I915_WRITE(DPIO_DATA, val);
> + I915_WRITE(DPIO_REG, reg);
> + I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
> + DPIO_BYTE);
> + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
> + DRM_ERROR("DPIO write wait timed out\n");
> +
> +out_unlock:
> + spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
> +}
> +
> +static void vlv_init_dpio(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /* Reset the DPIO config */
> + I915_WRITE(DPIO_CTL, 0);
> + POSTING_READ(DPIO_CTL);
> + I915_WRITE(DPIO_CTL, 1);
> + POSTING_READ(DPIO_CTL);
> +}
> +
> static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
> int refclk)
> {
> @@ -9306,6 +9364,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
What do you think about checking the busy bit at init time, and if it's
not clear we assume things are screwed and don't use dpio?
> if (IS_IRONLAKE_M(dev))
> ironlake_disable_rc6(dev);
>
> + if (IS_VALLEYVIEW(dev))
> + vlv_init_dpio(dev);
> +
> mutex_unlock(&dev->struct_mutex);
>
> /* Disable the irq before mode object teardown, for the irq might
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9cec6c3..07bcad0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -45,6 +45,18 @@
> ret__; \
> })
>
> +#define wait_for_atomic_us(COND, US) ({ \
> + int i, ret__ = -ETIMEDOUT; \
> + for (i = 0; i < (US); i++) { \
> + if ((COND)) { \
> + ret__ = 0; \
> + break; \
> + } \
> + udelay(1); \
> + } \
> + ret__; \
> +})
> +
> #define wait_for(COND, MS) _wait_for(COND, MS, 1)
> #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
>
> @@ -419,4 +431,6 @@ extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
>
> +extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
> +
> #endif /* __INTEL_DRV_H__ */
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
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