[Intel-gfx] [PATCH 15/26] agp/intel: map more registers for use by the GTT code

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:57PM -0700, Jesse Barnes wrote:
> We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
> register for doing so is above the range we normally map.  Map the whole
> register space to make sure we can get it.
> 
> v2: only map the larger space on gen7+ (Daniel)
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
>  drivers/char/agp/intel-gtt.c |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 5cf47ac..269cb02 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void)
>  static int i9xx_setup(void)
>  {
>  	u32 reg_addr;
> +	int size = KB(512);
>  
>  	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
>  
>  	reg_addr &= 0xfff80000;
>  
> -	intel_private.registers = ioremap(reg_addr, 128 * 4096);
> +	if (INTEL_GTT_GEN >= 7)
> +		size = MB(2);
> +
> +	intel_private.registers = ioremap(reg_addr, size);
>  	if (!intel_private.registers)
>  		return -ENOMEM;
>  

Acked-by: Ben Widawsky <ben at bwidawsk.net>

Does this need to go in -fixes since it seems like a "fix" for IVB?

Also, just looking at the code, is offset still correct? Gen5, and Gen6
have 2MB, Gen4, and default have 512kb.