[Intel-gfx] [PATCH v2 1/3] drm/i915: add rc6 residency times to debugfs

[Daniel Vetter]

On Sun, Mar 25, 2012 at 05:33:27PM -0700, Ben Widawsky wrote:
> RC6 residency should be in intervals of 1.28us, and the counter wraps.
> Here is an example using awk to get the various RC6 and RC6+ residency
> times in seconds, since boot.
> 
> cat /sys/kernel/debug/dri/0/i915_drpc_info  | grep residency | awk -F':' -F' '  '{print $5 * 1.28 / 1000000}'
> 
> This is primarily for debug, and QA/application developers using the
> sysfs interface looking for more insight.
> 
> Untested on IVB.

Tested on my ivb, seems to yield sane numbers for the default
configuration (i.e. enable rc+rc6p, disable rc6pp).
-Daniel

> 
> v2: move comment to the correct place
> commeit message changes
> 
> CC: Ouping Zhang <ouping.zhang at intel.com>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> Reviewed-by (v1): Eugeni Dodonov <eugeni.dodonov at intel.com>
> Signed-off-by (v1): Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |   11 +++++++++++
>  drivers/gpu/drm/i915/i915_reg.h     |    5 +++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 66c90d4..4257151 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1133,6 +1133,17 @@ static int gen6_drpc_info(struct seq_file *m)
>  
>  	seq_printf(m, "Core Power Down: %s\n",
>  		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
> +
> +	/* Not exactly sure what this is */
> +	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %d\n",
> +		   I915_READ(GEN6_GT_GFX_RC6_LOCKED));
> +	seq_printf(m, "RC6 residency since boot: %d\n",
> +		   I915_READ(GEN6_GT_GFX_RC6));
> +	seq_printf(m, "RC6+ residency since boot: %d\n",
> +		   I915_READ(GEN6_GT_GFX_RC6p));
> +	seq_printf(m, "RC6++ residency since boot: %d\n",
> +		   I915_READ(GEN6_GT_GFX_RC6pp));
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f3609f2..b1c3d35 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3799,6 +3799,11 @@
>  						 GEN6_PM_RP_DOWN_THRESHOLD | \
>  						 GEN6_PM_RP_DOWN_TIMEOUT)
>  
> +#define GEN6_GT_GFX_RC6_LOCKED			0x138104
> +#define GEN6_GT_GFX_RC6				0x138108
> +#define GEN6_GT_GFX_RC6p			0x13810C
> +#define GEN6_GT_GFX_RC6pp			0x138110
> +
>  #define GEN6_PCODE_MAILBOX			0x138124
>  #define   GEN6_PCODE_READY			(1<<31)
>  #define   GEN6_READ_OC_PARAMS			0xc
> -- 
> 1.7.9.4
> 
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-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48