[Intel-gfx] [PATCH 12/37] drm/i915: add SBI registers
Rodrigo Vivi
rodrigo.vivi at gmail.com
Mon Mar 26 19:48:44 CEST 2012
Ops, actually I'm in doubt about this one, for me:
SBI_RESPONSE should be (0x0<<1)
SBI_READY should be (0x0<<0)
let's double check this togheter, otherwise:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
On Mon, Mar 26, 2012 at 2:40 PM, Rodrigo Vivi <rodrigo.vivi at gmail.com> wrote:
> * indentation
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
>
> On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
> <eugeni.dodonov at intel.com> wrote:
>> Those are responsible for the Sideband Interface programming.
>>
>> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 0af47b4..4ee8965 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3947,4 +3947,14 @@
>> #define DDI_BUF_TRANS_D 0x64F20
>> #define DDI_BUF_TRANS_E 0x64F80
>>
>> +/* Sideband Interface (SBI) is programmed indirectly, via
>> + * SBI_ADDR, which contains the register offset; and SBI_DATA,
>> + * which contains the payload */
>> +#define SBI_ADDR 0xC6000
>> +#define SBI_DATA 0xC6004
>> +#define SBI_CTL_STAT 0xC6008
>> +#define SBI_CTL_OP_CRRD (0x6<<8)
>> +#define SBI_CTL_OP_CRWR (0x7<<8)
>> +#define SBI_RESPONSE (0x1<<1)
>> +#define SBI_READY (0x1<<0)
>> #endif /* _I915_REG_H_ */
>> --
>> 1.7.9.2
>>
>> _______________________________________________
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>> Intel-gfx at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> GPG: 0x905BE242 @ wwwkeys.pgp.net
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net
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