[Intel-gfx] [PATCH 20/26] drm/i915: ValleyView has limited cacheability

Jesse Barnes jbarnes at virtuousgeek.org
Wed Mar 28 19:43:02 CEST 2012

On Mon, 26 Mar 2012 20:49:45 +0200
Daniel Vetter <daniel at ffwll.ch> wrote:

> On Mon, Mar 26, 2012 at 11:34:21AM -0700, Ben Widawsky wrote:
> > On Thu, Mar 22, 2012 at 02:39:02PM -0700, Jesse Barnes wrote:
> > > The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
> > > it does writes, so we can't use the cache bits the same way.
> > 
> > I found this commit message to be confusing. Is it simply saying CPU
> > writes are snooped by the GT, but GT writes are not snooped bv the CPU?
> > 
> > > 
> > > So map the status and pipe control pages as uncached on ValleyView, and
> > > only set the pages to cached if we're on a supported platform.
> > 
> > I'd like to see in the commit message why the pipe control page needs to
> > be uncached. The only workarounds on the top of my head don't care about
> > the coherency.
> Afaik we've cleared this up in our mtg yesterday:
> - Full coherent gtt mappings work, they simply moved the bit around (we
>   need to set bit2 instead of bit1 like on snb/ivb).
> - It sounds like all the gpu functions can handle coherent memory, like
>   on snb/ivb. But because there's no shared cache between the gpu and the
>   cpu you don't gain anything, but only lose due to the required snoop
>   traffic.
> - Because there's no last level cache it also means that when the gpu does
>   a write and snoops the cpu cache, it essentially means the cpu
>   completely drops it's cacheline and has to go back to main memory
>   (instead of l3 like it does on llc platforms). Gpu reads snoop the cpu
>   cache corectly.
> I hope this clears up the confusion around coherency on vlv. Let Jesse
> only needs to check with a real piece of silicon whether that's true ;-)
> -Daniel

Right, this patch is bogus; VLV should be just as capable here, so we
can drop this one and I'll verify the cache bits.

Jesse Barnes, Intel Open Source Technology Center
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