[Intel-gfx] [PATCH 04/22] drm/i915: interrupt bit definitions for VLV

[Daniel Vetter]

This patch looks more like a random set of registers than interrupt
definitions. Also it's missing the sob line. Please clarify a bit what
this is about.
-Daniel

On Wed, Mar 28, 2012 at 01:39:24PM -0700, Jesse Barnes wrote:
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   41 +++++++++++++++++++++++++++++++++++++++
>  1 files changed, 41 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7abdc15..68a02bd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2427,23 +2427,30 @@
>  #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
>  #define _PIPEASTAT		0x70024
>  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
> +#define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
>  #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
>  #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
>  #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
> +#define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
>  #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
>  #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
>  #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
>  #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
> +#define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<26)
>  #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
>  #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
>  #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
>  #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
>  #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
>  #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
> +#define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
>  #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
> +#define   SPRITE1_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
> +#define   SPRITE0_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
>  #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
>  #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
>  #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
> +#define   PLANE_FLIPDONE_INT_STATUS_VLV		(1UL<<10)
>  #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
>  #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
>  #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
> @@ -2468,6 +2475,40 @@
>  #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
>  #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
>  
> +#define DPFLIPSTAT_VLV				0x70028
> +#define   PIPEB_LINE_COMPARE_STATUS		(1<<29)
> +#define   PIPEB_HLINE_INT_EN			(1<<28)
> +#define   PIPEB_VBLANK_INT_EN			(1<<27)
> +#define   SPRITED_FLIPDONE_INT_EN		(1<<26)
> +#define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
> +#define   PLANEB_FLIPDONE_INT_EN		(1<<24)
> +#define   PIPEA_LINE_COMPARE_STATUS		(1<<21)
> +#define   PIPEA_HLINE_INT_EN			(1<<20)
> +#define   PIPEA_VBLANK_INT_EN			(1<<19)
> +#define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
> +#define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
> +#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
> +
> +#define DPINVGTT				0x7002c /* VLV only */
> +#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
> +#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
> +#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
> +#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
> +#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
> +#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
> +#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
> +#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
> +#define   DPINVGTT_EN_MASK			0xff0000
> +#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
> +#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
> +#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
> +#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
> +#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
> +#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
> +#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
> +#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
> +#define   DPINVGTT_STATUS_MASK			0xff
> +
>  #define DSPARB			0x70030
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
>  #define   DSPARB_CSTART_SHIFT	7
> -- 
> 1.7.5.4
> 
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-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48