[Intel-gfx] [RFC] drm/i915: opencode get/put irq for gen6+

Ben Widawsky ben at bwidawsk.net
Thu Mar 29 21:26:49 CEST 2012


Before Chris get's all mad and complains that I did the opposite with
semaphores - semaphores did have a bit of logic which many had found
confusing and it was greatly simplified by abstracting it.

Anyhow, this removes a few lines that really didn't serve much purpose.

It also seems I can collapse the GT and GEN6 interrupt definitions into
1, but I'll have to check, and it's a separate patch anyway.

Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |   80 ++++++++-----------------------
 drivers/gpu/drm/i915/intel_ringbuffer.h |    1 +
 2 files changed, 21 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b7b50a5..7e4b18c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -788,10 +788,12 @@ ring_add_request(struct intel_ring_buffer *ring,
 }
 
 static bool
-gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+gen6_ring_get_irq(struct intel_ring_buffer *ring)
 {
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 gflag = ring->irq_enable[0];
+	u32 rflag = ring->irq_enable[1];
 
 	if (!dev->irq_enabled)
 	       return false;
@@ -813,10 +815,12 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 }
 
 static void
-gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+gen6_ring_put_irq(struct intel_ring_buffer *ring)
 {
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 gflag = ring->irq_enable[0];
+	u32 rflag = ring->irq_enable[1];
 
 	spin_lock(&ring->irq_lock);
 	if (--ring->irq_refcount == 0) {
@@ -1285,6 +1289,8 @@ static const struct intel_ring_buffer render_ring = {
 	.get_seqno		= ring_get_seqno,
 	.irq_get		= render_ring_get_irq,
 	.irq_put		= render_ring_put_irq,
+	.irq_enable		= {GT_USER_INTERRUPT,
+				   GEN6_RENDER_USER_INTERRUPT},
 	.dispatch_execbuffer	= render_ring_dispatch_execbuffer,
 	.cleanup		= render_ring_cleanup,
 	.sync_to		= render_ring_sync_to,
@@ -1373,38 +1379,6 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 	return 0;
 }
 
-static bool
-gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
-{
-	return gen6_ring_get_irq(ring,
-				 GT_USER_INTERRUPT,
-				 GEN6_RENDER_USER_INTERRUPT);
-}
-
-static void
-gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
-{
-	return gen6_ring_put_irq(ring,
-				 GT_USER_INTERRUPT,
-				 GEN6_RENDER_USER_INTERRUPT);
-}
-
-static bool
-gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
-{
-	return gen6_ring_get_irq(ring,
-				 GT_GEN6_BSD_USER_INTERRUPT,
-				 GEN6_BSD_USER_INTERRUPT);
-}
-
-static void
-gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
-{
-	return gen6_ring_put_irq(ring,
-				 GT_GEN6_BSD_USER_INTERRUPT,
-				 GEN6_BSD_USER_INTERRUPT);
-}
-
 /* ring buffer for Video Codec for Gen6+ */
 static const struct intel_ring_buffer gen6_bsd_ring = {
 	.name			= "gen6 bsd ring",
@@ -1416,8 +1390,10 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
 	.flush			= gen6_ring_flush,
 	.add_request		= gen6_add_request,
 	.get_seqno		= gen6_ring_get_seqno,
-	.irq_get		= gen6_bsd_ring_get_irq,
-	.irq_put		= gen6_bsd_ring_put_irq,
+	.irq_enable		= {GT_GEN6_BSD_USER_INTERRUPT,
+				  GEN6_BSD_USER_INTERRUPT},
+	.irq_get		= gen6_ring_get_irq,
+	.irq_put		= gen6_ring_put_irq,
 	.dispatch_execbuffer	= gen6_ring_dispatch_execbuffer,
 	.sync_to		= gen6_bsd_ring_sync_to,
 	.semaphore_register	= {MI_SEMAPHORE_SYNC_VR,
@@ -1426,24 +1402,6 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
 	.signal_mbox		= {GEN6_RVSYNC, GEN6_BVSYNC},
 };
 
-/* Blitter support (SandyBridge+) */
-
-static bool
-blt_ring_get_irq(struct intel_ring_buffer *ring)
-{
-	return gen6_ring_get_irq(ring,
-				 GT_BLT_USER_INTERRUPT,
-				 GEN6_BLITTER_USER_INTERRUPT);
-}
-
-static void
-blt_ring_put_irq(struct intel_ring_buffer *ring)
-{
-	gen6_ring_put_irq(ring,
-			  GT_BLT_USER_INTERRUPT,
-			  GEN6_BLITTER_USER_INTERRUPT);
-}
-
 static int blt_ring_flush(struct intel_ring_buffer *ring,
 			  u32 invalidate, u32 flush)
 {
@@ -1475,8 +1433,10 @@ static const struct intel_ring_buffer gen6_blt_ring = {
 	.flush			= blt_ring_flush,
 	.add_request		= gen6_add_request,
 	.get_seqno		= gen6_ring_get_seqno,
-	.irq_get		= blt_ring_get_irq,
-	.irq_put		= blt_ring_put_irq,
+	.irq_enable		= {GT_BLT_USER_INTERRUPT,
+				   GEN6_BLITTER_USER_INTERRUPT},
+	.irq_get		= gen6_ring_get_irq,
+	.irq_put		= gen6_ring_put_irq,
 	.dispatch_execbuffer	= gen6_ring_dispatch_execbuffer,
 	.sync_to		= gen6_blt_ring_sync_to,
 	.semaphore_register	= {MI_SEMAPHORE_SYNC_BR,
@@ -1494,8 +1454,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen >= 6) {
 		ring->add_request = gen6_add_request;
 		ring->flush = gen6_render_ring_flush;
-		ring->irq_get = gen6_render_ring_get_irq;
-		ring->irq_put = gen6_render_ring_put_irq;
+		ring->irq_get = gen6_ring_get_irq;
+		ring->irq_put = gen6_ring_put_irq;
 		ring->get_seqno = gen6_ring_get_seqno;
 	} else if (IS_GEN5(dev)) {
 		ring->add_request = pc_render_add_request;
@@ -1518,8 +1478,8 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
 	*ring = render_ring;
 	if (INTEL_INFO(dev)->gen >= 6) {
 		ring->add_request = gen6_add_request;
-		ring->irq_get = gen6_render_ring_get_irq;
-		ring->irq_put = gen6_render_ring_put_irq;
+		ring->irq_get = gen6_ring_get_irq;
+		ring->irq_put = gen6_ring_put_irq;
 	} else if (IS_GEN5(dev)) {
 		ring->add_request = pc_render_add_request;
 		ring->get_seqno = pc_render_get_seqno;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index bc0365b..278492a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -59,6 +59,7 @@ struct  intel_ring_buffer {
 	spinlock_t	irq_lock;
 	u32		irq_refcount;
 	u32		irq_mask;
+	u32		irq_enable[2];
 	u32		irq_seqno;		/* last seq seem at irq time */
 	u32		trace_irq_seqno;
 	u32		waiting_seqno;
-- 
1.7.9.5




More information about the Intel-gfx mailing list