[Intel-gfx] [PATCH 1/7] drm/i915: implement ColorBlt w/a

Chris Wilson chris at chris-wilson.co.uk
Sat Mar 31 15:15:21 CEST 2012

On Sat, 31 Mar 2012 11:54:01 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> On Sat, 31 Mar 2012 11:21:57 +0200, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> > According to an internal workaround master list, we need to set bit 5
> > of register 9400 to avoid issues with color blits.
> This sounds like it could be the root cause behind the FBC + BLT hangs.

This looks like it could be true, I just tested the w/a with the FBC
enabled and it survives!

Tested-by: Chris Wilson <chris at chris-wilson.co.uk>

I'm fully expecting it to blow up later, but one step forward.

Chris Wilson, Intel Open Source Technology Centre

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