[Intel-gfx] [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function

[Daniel Vetter]

On Thu, Oct 25, 2012 at 12:15:48PM -0700, Jesse Barnes wrote:
> So we can write them properly.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>

Slurped in the entire series, thanks for the patches.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c |    9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d4b3507..fb4b816 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1129,8 +1129,17 @@ static bool IS_DISPLAYREG(u32 reg)
>  		return false;
>  
>  	switch (reg) {
> +	case _3D_CHICKEN3:
> +	case IVB_CHICKEN3:
> +	case GEN7_COMMON_SLICE_CHICKEN1:
> +	case GEN7_L3CNTLREG1:
> +	case GEN7_L3_CHICKEN_MODE_REGISTER:
>  	case GEN7_ROW_CHICKEN2:
> +	case GEN7_L3SQCREG4:
> +	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
>  	case GEN7_HALF_SLICE_CHICKEN1:
> +	case GEN6_MBCTL:
> +	case GEN6_UCGCTL2:
>  		return false;

/me screams

>  	default:
>  		break;
> -- 
> 1.7.9.5
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch