[Intel-gfx] [PATCH] drm/i915: Only check for valid PP_{ON, OFF}_DELAYS on pre ILK hardware

[Paulo Zanoni]

Hi

2012/11/1 Daniel Vetter <daniel at ffwll.ch>:
> On Thu, Nov 1, 2012 at 4:52 PM, Paulo Zanoni <przanoni at gmail.com> wrote:
>> The only problem is: we're not doing anything here for the
>> HAS_PCH_SPLIT platforms. Shouldn't we be doing something? We do have
>> eDP code to set the PCH_PP registers, but not LVDS code for this.
>> Also, each encoder probably needs different values.
>>
>> So my suggestion would be: apply this patch (since it fixes a problem)
>> and then, in the future, maybe, move this code to the encoder-specific
>> callbacks, and also consider the HAS_PCH_SPLIT + LVDS case.
>
> It's even worse than that: This code is also run on ums setups, so
> potentially we could break some old setups here ...

I certainly understand how the suggestion I made may break the UMS
setup, so I really think we can "drop" my suggestion, but I see no
reason to drop the original patch, since it just avoids writing a
register that does not exist (giving us less error messages on
Haswell). Maybe this patch was just forgotten?

> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Paulo Zanoni