[Intel-gfx] [PATCH 7/8] drm/i915: enable intel_lvds->pre_pll_enable for ilk+, too

[Paulo Zanoni]

Hi

2012/11/5 Daniel Vetter <daniel.vetter at ffwll.ch>:
> Only two things needed adjustment:
> - pipe select for PCH_CPT
> - There's no dithering bit on ilk+ in the lvds ctl reg
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 40 ------------------------------------
>  drivers/gpu/drm/i915/intel_lvds.c    | 24 ++++++++++++++--------
>  2 files changed, 15 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bd3fa2b..68c0524 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5324,7 +5324,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>         bool ok, has_reduced_clock = false;
>         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
>         struct intel_encoder *encoder;
> -       u32 temp;
>         int ret;
>         bool dither, fdi_config_ok;
>
> @@ -5387,45 +5386,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>         } else
>                 intel_put_pch_pll(intel_crtc);
>
> -       /* The LVDS pin pair needs to be on before the DPLLs are enabled.
> -        * This is an exception to the general rule that mode_set doesn't turn
> -        * things on.
> -        */
> -       if (is_lvds) {
> -               temp = I915_READ(PCH_LVDS);
> -               temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> -               if (HAS_PCH_CPT(dev)) {
> -                       temp &= ~PORT_TRANS_SEL_MASK;
> -                       temp |= PORT_TRANS_SEL_CPT(pipe);
> -               } else {
> -                       if (pipe == 1)
> -                               temp |= LVDS_PIPEB_SELECT;
> -                       else
> -                               temp &= ~LVDS_PIPEB_SELECT;
> -               }
> -
> -               /* set the corresponsding LVDS_BORDER bit */
> -               temp |= dev_priv->lvds_border_bits;
> -               /* Set the B0-B3 data pairs corresponding to whether we're going to
> -                * set the DPLLs for dual-channel mode or not.
> -                */
> -               if (clock.p2 == 7)
> -                       temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> -               else
> -                       temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> -
> -               /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> -                * appropriately here, but we need to look more thoroughly into how
> -                * panels behave in the two modes.
> -                */
> -               temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> -               if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
> -                       temp |= LVDS_HSYNC_POLARITY;
> -               if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
> -                       temp |= LVDS_VSYNC_POLARITY;
> -               I915_WRITE(PCH_LVDS, temp);
> -       }
> -
>         if (is_dp && !is_cpu_edp) {
>                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
>         } else {
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 057e29a..b4025c1 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -104,17 +104,20 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
>         int pipe = intel_crtc->pipe;
>         u32 temp;
>
> -       /* pch split platforms are not yet converted. */
> -       if (HAS_PCH_SPLIT(dev))
> -               return;
> -
>         temp = I915_READ(lvds_encoder->reg);
>         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> -       if (pipe == 1) {
> -               temp |= LVDS_PIPEB_SELECT;
> +
> +       if (HAS_PCH_CPT(dev)) {
> +               temp &= ~PORT_TRANS_SEL_MASK;
> +               temp |= PORT_TRANS_SEL_CPT(pipe);
>         } else {
> -               temp &= ~LVDS_PIPEB_SELECT;
> +               if (pipe == 1) {
> +                       temp |= LVDS_PIPEB_SELECT;
> +               } else {
> +                       temp &= ~LVDS_PIPEB_SELECT;
> +               }
>         }
> +
>         /* set the corresponsding LVDS_BORDER bit */
>         temp |= dev_priv->lvds_border_bits;
>         /* Set the B0-B3 data pairs corresponding to whether we're going to
> @@ -129,8 +132,11 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
>          * appropriately here, but we need to look more thoroughly into how
>          * panels behave in the two modes.
>          */
> -       /* set the dithering flag on LVDS as needed */
> -       if (INTEL_INFO(dev)->gen >= 4) {
> +
> +       /* Set the dithering flag on LVDS as needed, note that there is no
> +        * special lvds dither control bit on pch-split platforms, dithering is
> +        * only controlled through the PIPECONF reg. */
> +       if (INTEL_INFO(dev)->gen == 4) {
>                 if (dev_priv->lvds_dither)
>                         temp |= LVDS_ENABLE_DITHER;
>                 else
> --
> 1.7.11.7
>
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-- 
Paulo Zanoni