[Intel-gfx] [PATCH] drm/i915: Write the FDI RX TU size reg at the right time

[Daniel Vetter]

According to "Graphics BSpec: vol4g North Display Engine Registers [IVB],
Display Mode Set Sequence" We need to write the TU size register
of the fdi RX unit _before_ starting to train the link.

v2: Paulo Zanoni pointed out that the current sequence is already
corret - I've been confused by the _very_ early call of fdi_pll_enable
in the enable sequence in our code. Hence just clarify the comment.

In the future we might want to move the fdi_pll_enable call to the
other fdi/pch resource enabling in enable_transcoder, but that's a
larger rework.

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0261d18..78f8481 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2681,7 +2681,8 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
 	int pipe = intel_crtc->pipe;
 	u32 reg, temp;
 
-	/* Write the TU size bits so error detection works */
+	/* Write the TU size bits so error detection works. This must be done
+	 * before we start to train the fdi links. */
 	I915_WRITE(FDI_RX_TUSIZE1(pipe),
 		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
 
-- 
1.7.11.4