[Intel-gfx] [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

[Daniel Vetter]

On Sat, Oct 27, 2012 at 3:18 PM, Paulo Zanoni <przanoni at gmail.com> wrote:
> Our mode set sequence says the FDI PLL should be enabled way earlier
> than the other FDI/PCH resources, and that's what we currently do, so
> I believe it is currently being called at the "right place" or at
> least close to the right place. It seems RX TU_SIZE enablement is not
> part of the "FDI PLL enablement", but part of the "other FDI/PCH
> resources" enablement (at least that's that the HSW mode set sequence
> says), and that's why I agree with the patch.
>
> (I have the feeling I am trying to explain to you why your patch is correct...)
>
> Well, it's your patch, your choice :)

Ok, I've rechecked the modeset sequence, and we need to indeed enable
fdi plls _before_ we enable the cpu pipe. I think I'll merge v1, plus
throw another patch on top to explain why fdi_pll_enable is so damn
early.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch