[Intel-gfx] [PATCH 11/36] drm/i915: properly program FDI_RX_MISC pwrdn lane values on HSW

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

That's what our mode set sequence documentation says we need to do.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5d33f62..0239888 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -205,6 +205,12 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		POSTING_READ(_FDI_RXA_CTL);
 		udelay(100);
 
+		/* Program FDI_RX_MISC pwrdn lanes */
+		temp = I915_READ(_FDI_RXA_MISC);
+		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+		I915_WRITE(_FDI_RXA_MISC, temp);
+		POSTING_READ(_FDI_RXA_MISC);
+
 		temp = I915_READ(DP_TP_STATUS(PORT_E));
 		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 			DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
@@ -227,6 +233,14 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 			rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
 			I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+
+			temp = I915_READ(_FDI_RXA_MISC);
+			temp &= ~(FDI_RX_PWRDN_LANE1_MASK |
+				  FDI_RX_PWRDN_LANE0_MASK);
+			temp |= FDI_RX_PWRDN_LANE1_VAL(2) |
+				FDI_RX_PWRDN_LANE0_VAL(2);
+			I915_WRITE(_FDI_RXA_MISC, temp);
+
 			continue;
 		}
 	}
-- 
1.7.11.4