[Intel-gfx] [PATCH 12/36] drm/i915: wait only 35us for the FDI link training

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

First we wait 30us for the FDI receiver lane calibration, then we wait
5us for the FDI auto training time.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0239888..11b5809 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -203,7 +203,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 		POSTING_READ(_FDI_RXA_CTL);
-		udelay(100);
+
+		/* Wait for FDI receiver lane calibration */
+		udelay(30);
 
 		/* Program FDI_RX_MISC pwrdn lanes */
 		temp = I915_READ(_FDI_RXA_MISC);
@@ -211,6 +213,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(_FDI_RXA_MISC, temp);
 		POSTING_READ(_FDI_RXA_MISC);
 
+		/* Wait for FDI auto training time */
+		udelay(5);
+
 		temp = I915_READ(DP_TP_STATUS(PORT_E));
 		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 			DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
-- 
1.7.11.4