[Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

[Ben Widawsky]

Apparently these ECOCHK bits changed on HSW and the behavior is not what
we want. I've not been able to find VLV definition specifically so I'll
assume it's the same as IVB.

(Only compile tested)

Reported-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4cbae7b..01cf805 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -322,11 +322,11 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
 		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 				       ECOCHK_PPGTT_CACHE64B);
 		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-	} else if (INTEL_INFO(dev)->gen >= 7) {
+	} else if (INTEL_INFO(dev)->gen >= 7 && !IS_HASWELL(dev)) {
 		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
-		/* GFX_MODE is per-ring on gen7+ */
 	}
 
+	/* GFX_MODE is per-ring on gen7+ */
 	for_each_ring(ring, dev_priv, i) {
 		if (INTEL_INFO(dev)->gen >= 7)
 			I915_WRITE(RING_MODE_GEN7(ring),
-- 
1.8.2