[Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

[Ben Widawsky]

On Wed, Apr 03, 2013 at 01:41:05PM -0700, Ben Widawsky wrote:
> On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote:
> > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter <daniel at ffwll.ch> wrote:
> > > So I've checked hsw bspec and the problem is that hw guys again
> > > changed the bits around a bit, and I think on HSW we actually want
> > > (0x8 << 3) instead of what's currently there.
> > 
> > Meh, I've screwed up reading the tables, 0x3 << 3 is what we imo want,
> > so nothing needs to be changed. Sorry for the confusion.
> > -Daniel
> 
> I think the existing code is magic that we don't/shouldn't need. But I
> also see no reason to change it.

Digging a bit more, it seems we want this for GEN6 (setting 3<<3), but
not GEN7. I'm done digging now.

-- 
Ben Widawsky, Intel Open Source Technology Center